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Masking at Gate Level in the Presence of Glitches
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Differential Power Analysis in the Presence of Hardware Countermeasures
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Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies
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Securing the AES Finalists Against Power Analysis Attacks
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Electromagnetic Analysis: Concrete Results
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An Implementation of DES and AES, Secure against Some Attacks
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Power Analysis Attacks of Modular Exponentiation in Smartcards
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DES and Differential Power Analysis The “Duplication” Method
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Resistance Against Differential Power Analysis For Elliptic Curve Cryptosystems
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Towards Sound Approaches to Counteract Power-Analysis Attacks
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Hardware Countermeasures against DPA – A Statistical Analysis of Their Effectiveness
inferredcites →https://doi.org/10.1007/978-3-540-25937-4_21openalex-snapshot
Two Power Analysis Attacks against One-Mask Methods
inferredcites →https://doi.org/10.1007/978-3-540-30564-4_5openalex-snapshot
Provably Secure Masking of AES
inferredcites →https://doi.org/10.1007/978-3-540-30574-3_24openalex-snapshot
Side-Channel Leakage of Masked CMOS Gates
inferredcites →https://doi.org/10.1007/978-3-540-45146-4_27openalex-snapshot
Private Circuits: Securing Hardware against Probing Attacks
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_11openalex-snapshot
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
inferredcites →https://doi.org/10.1049/el:20040385openalex-snapshot
Universal masking on logic gate level
inferredcites →https://doi.org/10.1109/date.2004.1268856openalex-snapshot
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
inferredcites →https://doi.org/10.1109/tc.2002.1004593openalex-snapshot
Examining smart-card security under the threat of power analysis attacks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Successfully Attacking Masked AES Hardware Implementations
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Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
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Threshold Implementations Against Side-Channel Attacks and Glitches
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Differential Power Analysis of Stream Ciphers
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Counteracting Power Analysis Attacks by Masking
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Minimizing S-Boxes in Hardware by Utilizing Linear Transformations
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A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks
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Codes for Side-Channel Attacks and Protections
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Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_6openalex-snapshot
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_8openalex-snapshot
DPA-Resistance Without Routing Constraints?
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A Near Optimal S-Box Design
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On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices
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Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
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A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
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Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs
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Survey of Methods to Improve Side-Channel Resistance on Partial Reconfigurable Platforms
inferred← citeshttps://doi.org/10.1007/978-3-642-21040-2_14openalex-snapshot
Leakage Squeezing Countermeasure against High-Order Attacks
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A Novel Circuit Design Methodology to Reduce Side Channel Leakage
inferred← citeshttps://doi.org/10.1007/978-3-662-44709-3_32openalex-snapshot
Gate-Level Masking under a Path-Based Leakage Metric
inferred← citeshttps://doi.org/10.1007/978-94-007-1338-3_4openalex-snapshot
Countermeasures Against Physical Attacks in FPGAs
inferred← citeshttps://doi.org/10.1007/s00145-010-9085-7openalex-snapshot
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches
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Achieving side-channel high-order correlation immunity with leakage squeezing
inferred← citeshttps://doi.org/10.1016/j.iot.2022.100655openalex-snapshot
Processor power and energy consumption estimation techniques in IoT applications: A review
inferred← citeshttps://doi.org/10.1049/iet-ifs:20070066openalex-snapshot
Security analysis of higher-order Boolean masking schemes for block ciphers (with conditions of perfect masking)
inferred← citeshttps://doi.org/10.1049/iet-ifs:20080041openalex-snapshot
Effect of glitches against masked AES S-box implementation and countermeasure
inferred← citeshttps://doi.org/10.1109/ecctd.2009.5275004openalex-snapshot
Differential power analysis of AES ASIC implementations with various S-box circuits
inferred← citeshttps://doi.org/10.1109/eleco.2009.5355223openalex-snapshot
A new power analysis resistant SRAM cell
inferred← citeshttps://doi.org/10.1109/fpt.2011.6269382openalex-snapshot
A Side-Channel hardened IP-Protection Scheme for FPGA-based Platforms
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412123openalex-snapshot
Side-channel resistant AES architecture utilizing randomized composite field representations
inferred← citeshttps://doi.org/10.1109/icicic.2007.612openalex-snapshot
Using Complement Register Structure Circuit against H-O DPA
inferred← citeshttps://doi.org/10.1109/icma.2007.4303897openalex-snapshot
A New Protect Cryptographic Circuit Approach Using Dynamic Current Model Logic Circuit
inferred← citeshttps://doi.org/10.1109/isicir.2011.6132007openalex-snapshot
Secret sharing based countermeasure for AES S-box
inferred← citeshttps://doi.org/10.1109/isvlsi.2017.44openalex-snapshot
Secured-by-Design FPGA against Early Evaluation
inferred← citeshttps://doi.org/10.1109/mape.2007.4393536openalex-snapshot
A New Methodology Protect Smart Cards from DPA
inferred← citeshttps://doi.org/10.1109/mwscas.2011.6026388openalex-snapshot
FPGA based optimization for masked AES implementation
inferred← citeshttps://doi.org/10.1109/mwscas.2016.7870159openalex-snapshot
Look-Up tables with multiple inputs for secured-by-design FPGAs
inferred← citeshttps://doi.org/10.1109/norchip.2015.7364404openalex-snapshot
Secured-by-design FPGA: look-up tables and switch-boxes
inferred← citeshttps://doi.org/10.1109/ntms.2019.8763813openalex-snapshot
FPGA Implementation of pAsynch Design Paradigm
inferred← citeshttps://doi.org/10.1109/securware.2010.43openalex-snapshot
Analyzing the DPA Leakage of the Masked S-box via Digital Simulation and Reducing the Leakage by Inserting Delay Cells
inferred← citeshttps://doi.org/10.1109/tc.2020.3022979openalex-snapshot
Hardware Private Circuits: From Trivial Composition to Full Verification
inferred← citeshttps://doi.org/10.1109/tdsc.2007.70234openalex-snapshot
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips
inferred← citeshttps://doi.org/10.1109/tifs.2020.3006399openalex-snapshot
Intrinsic Resiliency of S-Boxes Against Side-Channel Attacks–Best and Worst Scenarios
inferred← citeshttps://doi.org/10.1109/trustcom63139.2024.00176openalex-snapshot
Enhancing Higher-Order Masking: A Faster and Secure Implementation to Mitigate Bit Interaction Leakage
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2757064openalex-snapshot
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information
inferred← citeshttps://doi.org/10.1142/s0218126624502451openalex-snapshot
Power Attack Vulnerability Assessment of Circuit-Level PRESENT Encryption IP Using Artificial Intelligence Mechanisms
inferred← citeshttps://doi.org/10.1201/9780849387692.ch7openalex-snapshot
Side-Channel Analysis Attacks on Hardware Implementations of Cryptographic Algorithms
inferred← citeshttps://doi.org/10.13089/jkiisc.2014.24.1.221openalex-snapshot
Second-Order G-equivariant Logic Gate for AND Gate and its Application to Secure AES Implementation
inferred← citeshttps://doi.org/10.14722/ndss.2021.23137openalex-snapshot
Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers
inferred← citeshttps://doi.org/10.23919/date.2018.8342042openalex-snapshot
Embedded randomness and data dependencies design paradigm: Advantages and challenges
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774763openalex-snapshot
Leakage Power Analysis in Different S-Box Masking Protection Schemes
inferred← citeshttps://doi.org/10.26083/tuprints-00003374openalex-snapshot
Mutating Runtime Architectures as a Countermeasure Against Power Analysis Attacks
inferred← citeshttps://doi.org/10.3390/jlpea7010004openalex-snapshot
A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules
inferred← citeshttps://doi.org/10.4218/etrij.08.0107.0167openalex-snapshot
Differential Side Channel Analysis Attacks on FPGA Implementations of ARIA
inferred← citeshttps://doi.org/10.46586/tches.v2018.i3.89-120openalex-snapshot
Composable Masking Schemes in the Presence of Physical Defaults & the Robust Probing Model
inferred← citeshttps://doi.org/10.48550/arxiv.1103.1360openalex-snapshot
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
inferred← citeshttps://doi.org/10.48550/arxiv.2106.12714openalex-snapshot
Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners
inferred← citeshttps://doi.org/10.5555/1266366.1266643openalex-snapshot
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
inferred← citeshttps://doi.org/10.62056/aee0zoja5openalex-snapshot
Provably Secure and Area-Efficient Modular Addition over Boolean Shares
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