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Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/1-4020-8147-2_10openalex-snapshot
Place and Route for Secure Standard Cell Design
inferredcites →https://doi.org/10.1007/3-540-45472-1_12openalex-snapshot
Statistics and Secret Leakage
inferredcites →https://doi.org/10.1007/978-3-540-30574-3_24openalex-snapshot
Side-Channel Leakage of Masked CMOS Gates
inferredcites →https://doi.org/10.1007/978-3-540-45238-6openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2003
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_12openalex-snapshot
Security Evaluation of Asynchronous Circuits
inferredcites →https://doi.org/10.1007/b105222openalex-snapshot
Topics in Cryptology – CT-RSA 2005
inferredcites →https://doi.org/10.1016/s0141-9331(03)00092-9openalex-snapshot
Balanced self-checking asynchronous logic for smart card applications
inferredcites →https://doi.org/10.1109/date.2004.1268856openalex-snapshot
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
inferredcites →https://doi.org/10.1109/date.2005.44openalex-snapshot
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
inferredcites →https://doi.org/10.1109/esscir.2004.1356679openalex-snapshot
Towards an AES crypto-chip resistant to differential power analysis
inferredcites →https://doi.org/10.1109/msp.2006.51openalex-snapshot
Securing embedded systems
inferredcites →https://doi.org/10.1145/1057661.1057677openalex-snapshot
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
inferredcites →https://doi.org/10.1145/775832.775850openalex-snapshot
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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inferred← citeshttps://doi.org/10.26102/2310-6018/2018.23.4.034openalex-snapshot
TIMING ATTACKS ON INFORMATION IN UNTRUSTED ENVIRONMENTS
inferred← citeshttps://doi.org/10.31274/etd-180810-2225openalex-snapshot
RAKSHA:Reliable and Aggressive frameworK for System design using High-integrity Approaches
inferred← citeshttps://doi.org/10.3390/electronics14061114openalex-snapshot
An Energy Efficient and DPA Attack Resilient NCFET-Based S-Box Design for Secure and Lightweight SLIM Ciphers
inferred← citeshttps://doi.org/10.4028/www.scientific.net/aef.6-7.169openalex-snapshot
Insert Random Time-Delay Defense High Order Side-Channel Attack
inferred← citeshttps://doi.org/10.4028/www.scientific.net/aef.6-7.200openalex-snapshot
A Self-Healing Cryptosystem Design Prevent from Side-Channel Attack
inferred← citeshttps://doi.org/10.48084/etasr.11870openalex-snapshot
Design of an SLIM Cipher S-box with 8T-SRAM CiM for Energy-Efficient, Lightweight, and DPA Resistant Edge AI
inferred← citeshttps://doi.org/10.48550/arxiv.2104.08593openalex-snapshot
SoK: Design Tools for Side-Channel-Aware Implementations
inferred← citeshttps://doi.org/10.70675/62f1057dz5077z4c24z8b9cz9bf93e5c7d36openalex-snapshot
Evaluation d'injection de fautes Laser et conception de contre-mesures sur une architecture à faible consommation
inferred← citeshttps://doi.org/10.70675/b38fcc34z2bddz4b1cz953ez08661545dce7openalex-snapshot
Crypto-processor – architecture, programming and evaluation of the security
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