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A Very Compact S-Box for AES
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-36400-5_14openalex-snapshot
An Optimized S-Box Circuit Architecture for Low Power AES Design
inferredcites →https://doi.org/10.1007/3-540-44709-1_16openalex-snapshot
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
inferredcites →https://doi.org/10.1007/3-540-45682-1_15openalex-snapshot
A Compact Rijndael Hardware Architecture with S-Box Optimization
inferredcites →https://doi.org/10.1007/3-540-45760-7_6openalex-snapshot
An ASIC Implementation of the AES SBoxes
inferredcites →https://doi.org/10.1007/978-3-540-30574-3_22openalex-snapshot
A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_26openalex-snapshot
Very Compact FPGA Implementation of the AES Algorithm
inferredcites →https://doi.org/10.1016/s0924-6509(08)x7030-8openalex-snapshot
The Theory of Error-Correcting Codes
inferredcites →https://doi.org/10.1017/cbo9781139172769openalex-snapshot
Introduction to Finite Fields and their Applications
inferredcites →https://doi.org/10.1109/iccd.2002.1106754openalex-snapshot
A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture
inferredcites →https://doi.org/10.1145/611817.611848openalex-snapshot
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11796435_46openalex-snapshot
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
inferred← citeshttps://doi.org/10.1007/11894063_22openalex-snapshot
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
inferred← citeshttps://doi.org/10.1007/11908739_25openalex-snapshot
Low Power AES Hardware Architecture for Radio Frequency Identification
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_10openalex-snapshot
FPGA and ASIC Implementations of AES
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_12openalex-snapshot
Block Cipher Modes of Operation from a Hardware Implementation Perspective
inferred← citeshttps://doi.org/10.1007/978-0-387-71829-3_3openalex-snapshot
Secret Key Crypto Implementations
inferred← citeshttps://doi.org/10.1007/978-1-4419-0965-7_9openalex-snapshot
C/C++ Hardware Design for the Real World
inferred← citeshttps://doi.org/10.1007/978-3-030-03329-3_13openalex-snapshot
Attacks and Countermeasures for White-box Designs
inferred← citeshttps://doi.org/10.1007/978-3-030-05755-8_11openalex-snapshot
Fast Implementation for SM4 Cipher Algorithm Based on Bit-Slice Technology
inferred← citeshttps://doi.org/10.1007/978-3-030-15462-2_8openalex-snapshot
Yet Another Size Record for AES: A First-Order SCA Secure AES S-Box Based on $$\mathrm {GF}(2^8)$$ GF ( 2 8 ) Multiplication
inferred← citeshttps://doi.org/10.1007/978-3-030-15663-3_11openalex-snapshot
Pushing the Limits Further: Sub-Atomic AES
inferred← citeshttps://doi.org/10.1007/978-3-030-17653-2_10openalex-snapshot
XOR-Counts and Lightweight Multiplication with Fixed Elements in Binary Finite Fields
inferred← citeshttps://doi.org/10.1007/978-3-030-41702-4_5openalex-snapshot
Monomial Evaluation of Polynomial Functions Protected by Threshold Implementations
inferred← citeshttps://doi.org/10.1007/978-3-030-64834-3_24openalex-snapshot
Quantum Circuit Implementations of AES with Fewer Qubits
inferred← citeshttps://doi.org/10.1007/978-3-030-89915-8openalex-snapshot
Constructive Side-Channel Analysis and Secure Design
inferred← citeshttps://doi.org/10.1007/978-3-030-90567-5_7openalex-snapshot
Constructions of Iterative Near-MDS Matrices with the Lowest XOR Count
inferred← citeshttps://doi.org/10.1007/978-3-031-25319-5_6openalex-snapshot
Guarding the First Order: The Rise of AES Maskings
inferred← citeshttps://doi.org/10.1007/978-3-031-25319-5_8openalex-snapshot
Self-timed Masking: Implementing Masked S-Boxes Without Registers
inferred← citeshttps://doi.org/10.1007/978-3-031-30122-3_29openalex-snapshot
Robustness of Affine and Extended Affine Equivalent Surjective S-Box(es) Against Differential Cryptanalysis
inferred← citeshttps://doi.org/10.1007/978-3-031-51135-6_10openalex-snapshot
SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V
inferred← citeshttps://doi.org/10.1007/978-3-031-88661-4_17openalex-snapshot
Affine Equivalence-Based Key-Recovery Attacks on White-Box Implementations of the SM4 Block Cipher
inferred← citeshttps://doi.org/10.1007/978-3-031-91107-1_6openalex-snapshot
Constructing Quantum Implementations with the Minimal T-depth or Minimal Width and Their Applications
inferred← citeshttps://doi.org/10.1007/978-3-032-01799-4_9openalex-snapshot
Let’s Share a Secret: Share-Reduced Design of M&M for the AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-032-10536-3_26openalex-snapshot
Picking up the Fallen Mask: Breaking and Fixing the RS-Mask Countermeasure
inferred← citeshttps://doi.org/10.1007/978-3-032-15541-2_11openalex-snapshot
Protecting AES-128 Against First-Order Side-Channel Analysis in Micro-Architectures by Enforcing Threshold Implementation Principles
inferred← citeshttps://doi.org/10.1007/978-3-032-16342-4_21openalex-snapshot
Quantum Synthesis of Large S-Boxes: Heuristic and MILP-Based Transpiled-Depth Optimization
inferred← citeshttps://doi.org/10.1007/978-3-032-31130-6_9openalex-snapshot
Can We Tolerate Small Side-Channel Leakages: The Role of Registers in Glitch-Stopping Circuits
inferred← citeshttps://doi.org/10.1007/978-3-319-13039-2_18openalex-snapshot
A Very Compact FPGA Implementation of LED and PHOTON
inferred← citeshttps://doi.org/10.1007/978-3-319-13039-2_19openalex-snapshot
S-box Pipelining Using Genetic Algorithms for High-Throughput AES Implementations: How Fast Can We Go?
inferred← citeshttps://doi.org/10.1007/978-3-319-13039-2_22openalex-snapshot
Confused by Confusion: Systematic Evaluation of DPA Resistance of Various S-boxes
inferred← citeshttps://doi.org/10.1007/978-3-319-21476-4_6openalex-snapshot
Evaluating the Duplication of Dual-Rail Precharge Logics on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-319-29814-6_32openalex-snapshot
Higher-Order Masking Schemes for Simon
inferred← citeshttps://doi.org/10.1007/978-3-319-31271-2_16openalex-snapshot
Higher-Order Threshold Implementation of the AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-319-31271-2_17openalex-snapshot
Compact Implementations of Multi-Sbox Designs
inferred← citeshttps://doi.org/10.1007/978-3-319-31301-6_10openalex-snapshot
Exploring Energy Efficiency of Lightweight Block Ciphers
inferred← citeshttps://doi.org/10.1007/978-3-319-31517-1_8openalex-snapshot
Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware
inferred← citeshttps://doi.org/10.1007/978-3-319-31875-2_17openalex-snapshot
An Improved Masking Scheme for S-Box Software Implementations
inferred← citeshttps://doi.org/10.1007/978-3-319-44318-8_1openalex-snapshot
AES Datapaths on FPGAs: A State of the Art Analysis
inferred← citeshttps://doi.org/10.1007/978-3-319-49890-4_10openalex-snapshot
Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core
inferred← citeshttps://doi.org/10.1007/978-3-319-52153-4_6openalex-snapshot
An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order
inferred← citeshttps://doi.org/10.1007/978-3-319-54978-1_12openalex-snapshot
Techniques for Secure Data Transfer
inferred← citeshttps://doi.org/10.1007/978-3-319-56620-7_20openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-64647-3_3openalex-snapshot
Dissecting Leakage Resilient PRFs with Multivariate Localized EM Attacks
inferred← citeshttps://doi.org/10.1007/978-3-319-64647-3_4openalex-snapshot
Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation
inferred← citeshttps://doi.org/10.1007/978-3-319-64647-3_6openalex-snapshot
SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA
inferred← citeshttps://doi.org/10.1007/978-3-319-66787-4_20openalex-snapshot
Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-319-66787-4_33openalex-snapshot
Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives
inferred← citeshttps://doi.org/10.1007/978-3-319-69453-5_10openalex-snapshot
All the AES You Need on Cortex-M3 and M4
inferred← citeshttps://doi.org/10.1007/978-3-319-69453-5_5openalex-snapshot
Uniform First-Order Threshold Implementations
inferred← citeshttps://doi.org/10.1007/978-3-319-71667-1_15openalex-snapshot
Looting the LUTs: FPGA Optimization of AES and AES-like Ciphers for Authenticated Encryption
inferred← citeshttps://doi.org/10.1007/978-3-319-71667-1_20openalex-snapshot
Several Masked Implementations of the Boyar-Peralta AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-319-76953-0_22openalex-snapshot
High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained
inferred← citeshttps://doi.org/10.1007/978-3-319-89339-6_7openalex-snapshot
SCA-Resistance for AES: How Cheap Can We Go?
inferred← citeshttps://doi.org/10.1007/978-3-319-89641-0_14openalex-snapshot
A First-Order SCA Resistant AES Without Fresh Randomness
inferred← citeshttps://doi.org/10.1007/978-3-319-97916-8_4openalex-snapshot
Entropy Reduction for the Correlation-Enhanced Power Analysis Collision Attack
inferred← citeshttps://doi.org/10.1007/978-3-540-68164-9_2openalex-snapshot
Implementation of the AES-128 on Virtex-5 FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-540-68914-0_27openalex-snapshot
A Very Compact “Perfectly Masked” S-Box for AES
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_9openalex-snapshot
On the Power of Bitslice Implementation on Intel Core2 Processor
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Efficient Implementations of Some Tweakable Enciphering Schemes in Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1007/978-3-540-79263-5_11openalex-snapshot
Boosting AES Performance on a Tiny Processor Core
inferred← citeshttps://doi.org/10.1007/978-3-540-85053-3_21openalex-snapshot
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
inferred← citeshttps://doi.org/10.1007/978-3-540-85053-3_8openalex-snapshot
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
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Using Normal Bases for Compact Hardware Implementations of the AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-540-85893-5_15openalex-snapshot
A Practical DPA Countermeasure with BDD Architecture
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Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
inferred← citeshttps://doi.org/10.1007/978-3-642-04138-9_1openalex-snapshot
Faster and Timing-Attack Resistant AES-GCM
inferred← citeshttps://doi.org/10.1007/978-3-642-10838-9_15openalex-snapshot
A Comparative Study of Mutual Information Analysis under a Gaussian Assumption
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Efficient Secure Two-Party Computation with Untrusted Hardware Tokens (Full Version)*
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Embedded SFE: Offloading Server and Network Using Hardware Tokens
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Mixed Bases for Efficient Inversion in ${{\mathbb F}{((2^2)^2)}{2}}$ and Conversion Matrices of SubBytes of AES
inferred← citeshttps://doi.org/10.1007/978-3-642-15031-9_28openalex-snapshot
Provably Secure Higher-Order Masking of AES
inferred← citeshttps://doi.org/10.1007/978-3-642-15031-9_29openalex-snapshot
Algebraic Side-Channel Analysis in the Presence of Errors
inferred← citeshttps://doi.org/10.1007/978-3-642-15031-9_9openalex-snapshot
Correlation-Enhanced Power Analysis Collision Attack
inferred← citeshttps://doi.org/10.1007/978-3-642-19074-2_7openalex-snapshot
Cryptanalysis of CLEFIA Using Differential Methods with Cache Trace Patterns
inferred← citeshttps://doi.org/10.1007/978-3-642-20465-4_6openalex-snapshot
Pushing the Limits: A Very Compact and a Threshold Implementation of AES
inferred← citeshttps://doi.org/10.1007/978-3-642-22792-9_13openalex-snapshot
The PHOTON Family of Lightweight Hash Functions
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An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
inferred← citeshttps://doi.org/10.1007/978-3-642-30436-1_24openalex-snapshot
A Small Depth-16 Circuit for the AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-642-31410-0_17openalex-snapshot
SPN-Hash: Improving the Provable Resistance against Differential Collision Attacks
inferred← citeshttps://doi.org/10.1007/978-3-642-33027-8_12openalex-snapshot
Towards Super-Exponential Side-Channel Security with Efficient Leakage-Resilient PRFs
inferred← citeshttps://doi.org/10.1007/978-3-642-34117-5_4openalex-snapshot
Very Short Critical Path Implementation of AES with Direct Logic Gates
inferred← citeshttps://doi.org/10.1007/978-3-642-35404-5_22openalex-snapshot
Some Representations of the S-Box of Camellia in GF(((22)2)2)
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$\textnormal{\textsc{TWINE}}$: A Lightweight Block Cipher for Multiple Platforms
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Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl
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Putting together What Fits together - GrÆStl
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Strengths and Limitations of High-Resolution Electromagnetic Field Measurements for Side-Channel Analysis
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Impact of Sboxes Size upon Side Channel Resistance and Block Cipher Design
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Cancellation-Free Circuits in Unbounded and Bounded Depth
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Stealthy Dopant-Level Hardware Trojans
inferred← citeshttps://doi.org/10.1007/978-3-642-41332-2_7openalex-snapshot
Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures
inferred← citeshttps://doi.org/10.1007/978-3-662-43933-3_23openalex-snapshot
ALE: AES-Based Lightweight Authenticated Encryption
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Side-Channel Leakage through Static Power
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Gate-Level Masking under a Path-Based Leakage Metric
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Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
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Constructing S-boxes for Lightweight Cryptography with Feistel Structure
inferred← citeshttps://doi.org/10.1007/978-3-662-48324-4_22openalex-snapshot
Transient-Steady Effect Attack on Block Ciphers
inferred← citeshttps://doi.org/10.1007/978-3-662-48324-4_30openalex-snapshot
DPA, Bitslicing and Masking at 1 GHz
inferred← citeshttps://doi.org/10.1007/978-3-662-48324-4_4openalex-snapshot
Highly Efficient $$GF(2^8)$$ G F ( 2 8 ) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design
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Midori: A Block Cipher for Low Energy
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Reverse-Engineering the S-Box of Streebog, Kuznyechik and STRIBOBr1
inferred← citeshttps://doi.org/10.1007/978-3-662-53140-2_10openalex-snapshot
Masking AES with $$d+1$$ Shares in Hardware
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On the Multiplicative Complexity of Boolean Functions and Bitsliced Higher-Order Masking
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A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths
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Strong 8-bit Sboxes with Efficient Masking in Hardware
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A Tale of Two Shares: Why Two-Share Threshold Implementation Seems Worthwhile—and Why It Is Not
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HDNM8: A Round-8 High Diffusion Block Cipher with Nonlinear Mixing Function
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Differential Power Analysis: Attacks and Resisting Techniques
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Hardware Performance of the $$\Theta $$CB3 Algorithm
inferred← citeshttps://doi.org/10.1007/978-981-95-0172-4_2openalex-snapshot
PRNG-Oriented Side-Channel Security Evaluation for TI-AES
inferred← citeshttps://doi.org/10.1007/978-981-95-5096-8_13openalex-snapshot
StaMAC: Fault Protection via Stable-MAC Tags
inferred← citeshttps://doi.org/10.1007/978-981-95-5096-8_15openalex-snapshot
Quantum Circuit Synthesis for AES with Low DW-Cost
inferred← citeshttps://doi.org/10.1007/978-981-97-3756-7_9openalex-snapshot
Optimized Composite Field-Based Hardware Architectures for AES S-Box Using Logic Decomposition Techniques
inferred← citeshttps://doi.org/10.1007/978-981-97-8051-8_14openalex-snapshot
Nonlinearity in AES Subkey Scheduling—An Augmented Security
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Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches
inferred← citeshttps://doi.org/10.1007/s00145-012-9124-7openalex-snapshot
Logic Minimization Techniques with Applications to Cryptology
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Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version
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Lightweight implementation of AES for resource constrained environment
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Side-channel cryptographic attacks using pseudo-boolean optimization
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Fully homomorphic SIMD operations
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Homomorphic AES evaluation using the modified LTV scheme
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Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard
inferred← citeshttps://doi.org/10.1007/s10836-023-06076-5openalex-snapshot
New Second-order Threshold Implementation of Sm4 Block Cipher
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An enhanced method for constructing cryptographically strong dynamic S-boxes with high and invariant nonlinearity via extended affine transformations
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Quantum reversible circuit of AES-128
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Some efficient quantum circuit implementations of Camellia
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New quantum circuit implementations of SM4 and SM3
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Optimized quantum implementation of AES
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Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
inferred← citeshttps://doi.org/10.1007/s11265-013-0788-5openalex-snapshot
Performance Characterization of AES Datapath Architectures in 90-nm Standard Cell CMOS Technology
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Evaluation of a Modular Approach to AES Hardware Architecture and Optimization
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An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box
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High Throughput AES Algorithm Using Parallel Subbytes and MixColumn
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Right or wrong collision rate analysis without profiling: full-automatic collision fault attack
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Unbalanced sharing: a threshold implementation of SM4
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A small first-order DPA resistant AES implementation with no fresh randomness
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Novel quantum circuit implementation of Advanced Encryption Standard with low costs
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Monomial evaluation of polynomial functions protected by threshold implementations—with an illustration on AES—
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Related-key impossible differential cryptanalysis on lightweight cipher TWINE
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Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags
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An exploration of mechanisms for dynamic cryptographic instruction set extension
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Stealthy dopant-level hardware Trojans: extended version
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Strong 8-bit Sboxes with efficient masking in hardware extended version
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A review of lightweight block ciphers
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Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs
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Compact circuits for combined AES encryption/decryption
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Your rails cannot hide from localized EM: how dual-rail logic fails on FPGAs—extended version
inferred← citeshttps://doi.org/10.1007/s13389-018-0187-8openalex-snapshot
Highly efficient $$\textit{GF}(2^8)$$ GF ( 2 8 ) inversion circuit based on hybrid GF representations
inferred← citeshttps://doi.org/10.1007/s13389-020-00225-8openalex-snapshot
Template attacks on nano-scale CMOS devices
inferred← citeshttps://doi.org/10.1007/s13389-021-00265-8openalex-snapshot
Six shades lighter: a bit-serial implementation of the AES family
inferred← citeshttps://doi.org/10.1007/s13389-022-00301-1openalex-snapshot
SPSA: Semi-Permanent Stuck-At fault analysis of AES Rijndael SBox
inferred← citeshttps://doi.org/10.1007/s13389-025-00371-xopenalex-snapshot
Research and implementation of large-scale S-box for MK-3 algorithm based on polynomial basis: in FPGA
inferred← citeshttps://doi.org/10.1007/s13389-025-00388-2openalex-snapshot
First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES
inferred← citeshttps://doi.org/10.1007/s41635-017-0021-2openalex-snapshot
An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security
inferred← citeshttps://doi.org/10.1007/s41635-020-00100-2openalex-snapshot
A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs
inferred← citeshttps://doi.org/10.1007/s42835-019-00226-6openalex-snapshot
Securing the AES Cryptographic Circuit Against Both Power and Fault Attacks
inferred← citeshttps://doi.org/10.1007/s44291-026-00295-8openalex-snapshot
Control optimized AES-128 cryptographic architectures achieving 94.2% logic reduction and 50% power savings
inferred← citeshttps://doi.org/10.1007/s44443-025-00065-8openalex-snapshot
Efficient quantum circuit research and implementation for 16-bit S-boxes based on composite field
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2008.06.004openalex-snapshot
Dual-rail transition logic: A logic style for counteracting power analysis attacks
inferred← citeshttps://doi.org/10.1016/j.ffa.2014.10.008openalex-snapshot
A survey of some recent bit-parallel GF(2n) multipliers
inferred← citeshttps://doi.org/10.1016/j.future.2018.01.063openalex-snapshot
A tree search algorithm for low multiplicative complexity logic design
inferred← citeshttps://doi.org/10.1016/j.ipl.2018.04.010openalex-snapshot
Improved upper bounds for the expected circuit complexity of dense systems of linear equations over GF(2)
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A survey on lightweight block ciphers for low-resource devices: Comparative study and open issues
inferred← citeshttps://doi.org/10.1016/j.mejo.2025.106917openalex-snapshot
Compact fully-unrolled architectures for AES based on merging and combining of linear operations
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.06.014openalex-snapshot
A new zero value attack combined fault sensitivity analysis on masked AES
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103000openalex-snapshot
Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology
inferred← citeshttps://doi.org/10.1016/j.tcs.2014.10.014openalex-snapshot
Cancellation-free circuits in unbounded and bounded depth
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Vulnerability modeling of cryptographic hardware to power analysis attacks
inferred← citeshttps://doi.org/10.1016/j.vlsi.2012.06.002openalex-snapshot
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.05.003openalex-snapshot
Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems
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Efficient advanced encryption standard implementation using lookup and normal basis
inferred← citeshttps://doi.org/10.1049/iet-cdt.2019.0179openalex-snapshot
High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications
inferred← citeshttps://doi.org/10.1049/iet-ifs.2018.5244openalex-snapshot
New second‐order threshold implementation of AES
inferred← citeshttps://doi.org/10.1049/iet-ifs.2019.0602openalex-snapshot
Research on a high‐order AES mask anti‐power attack
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AES crypto processor with improved s-box for hardware acceleration
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Performance-efficient flexible architecture of m–Crypton cipher for resource-constrained applications
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Fast Inversions in Small Finite Fields by Using Binary Trees
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An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
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Continuous-Variable Arbitrated Quantum Signature Based on Dense Coding and Teleportation
inferred← citeshttps://doi.org/10.1109/access.2019.2942781openalex-snapshot
DPA Protected Implementation of OCB and COLM Authenticated Ciphers
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Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application
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An Efficient Generation and Security Analysis of Substitution Box Using Fingerprint Patterns
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VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic
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Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications
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Analysis of an 8-bit Serial Rijndael-256 FPGA Implementation
inferred← citeshttps://doi.org/10.1109/acssc.2017.8335570openalex-snapshot
Performance comparison of AES-GCM-SIV and AES-GCM algorithms for authenticated encryption on FPGA platforms
inferred← citeshttps://doi.org/10.1109/arith.2013.25openalex-snapshot
Another Look at Inversions over Binary Fields
inferred← citeshttps://doi.org/10.1109/arith.2016.32openalex-snapshot
Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2^4)^2 of GF(2^8)
inferred← citeshttps://doi.org/10.1109/arith.2018.8464780openalex-snapshot
New Area Record for the AES Combined S-Box/Inverse S-Box
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A Faster Hardware Implementation of the AES S-box
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Architectures for Sustainable Security in the Computing Continuum
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A high-throughput cost-effective ASIC implementation of the AES Algorithm
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A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices
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An Energy Efficient AES Encryption Core for Hardware Security Implementation in IoT Systems
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A low-power and cost-effective AES chip design for healthcare devices
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