On the public citation graph
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
0 signed · 103 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11424826_70openalex-snapshot
Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography
inferredcites →https://doi.org/10.1007/11502760_27openalex-snapshot
How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4 Processors
inferredcites →https://doi.org/10.1007/11552055_2openalex-snapshot
An Instruction Set Extension for Fast and Memory-Efficient AES Implementation
inferredcites →https://doi.org/10.1007/11799313_22openalex-snapshot
How Far Can We Go on the x64 Processors?
inferredcites →https://doi.org/10.1007/3-540-36400-5_13openalex-snapshot
Efficient Software Implementation of AES on 32-Bit Platforms
inferredcites →https://doi.org/10.1109/acssc.1994openalex-snapshot
Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers
inferredcites →https://doi.org/10.1109/acssc.2004.1399180openalex-snapshot
Interfacing a high speed crypto accelerator to an embedded CPU
inferredcites →https://doi.org/10.1109/asap.2003.1212838openalex-snapshot
Using media processors for low-memory AES implementation
inferredcites →https://doi.org/10.1109/asap.2005.49openalex-snapshot
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
inferredcites →https://doi.org/10.1109/asap.2006.62openalex-snapshot
Speeding Up AES By Extending a 32 bit Processor Instruction Set
inferredcites →https://doi.org/10.1109/ipdps.2004.1303110openalex-snapshot
Embedded software integration for coarse-grain reconfigurable systems
inferredcites →https://doi.org/10.1109/isca.2001.937439openalex-snapshot
CryptoManiac: a fast flexible architecture for secure communication
inferredcites →https://doi.org/10.1109/sips.2004.1363041openalex-snapshot
Extended instructions for the aes cryptography and their efficient implementation
inferredcites →https://doi.org/10.1145/356989.357006openalex-snapshot
Architectural support for fast symmetric-key cryptography
inferredcites →https://doi.org/10.1145/378993.379238openalex-snapshot
Architectural support for fast symmetric-key cryptography
inferredcites →https://doi.org/10.1145/513918.514113openalex-snapshot
System design methodologies for a wireless security processing platform
inferredcites →https://doi.org/10.1145/951710.951738openalex-snapshot
AES and the cryptonite crypto processor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/sec.555openalex-snapshot
Design and implementation of a versatile cryptographic unit for RISC processors
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_9openalex-snapshot
Instruction Set Extensions for Cryptographic Applications
inferred← citeshttps://doi.org/10.1007/978-1-4614-7915-4_5openalex-snapshot
Hardware and VLSI Designs
inferred← citeshttps://doi.org/10.1007/978-3-319-31875-2_26openalex-snapshot
Structured Design Approach for an Optimal Programmable Synchronous Security Processor
inferred← citeshttps://doi.org/10.1007/978-3-540-72738-5_10openalex-snapshot
Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis
inferred← citeshttps://doi.org/10.1007/978-3-540-73074-3_5openalex-snapshot
VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_21openalex-snapshot
Power Analysis Resistant AES Implementation with Instruction Set Extensions
inferred← citeshttps://doi.org/10.1007/978-3-540-79263-5_11openalex-snapshot
Boosting AES Performance on a Tiny Processor Core
inferred← citeshttps://doi.org/10.1007/978-3-540-85053-3_21openalex-snapshot
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
inferred← citeshttps://doi.org/10.1007/978-3-642-03317-9_4openalex-snapshot
Intel’s New AES Instructions for Enhanced Performance and Security
inferred← citeshttps://doi.org/10.1007/978-3-642-04138-9_15openalex-snapshot
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
inferred← citeshttps://doi.org/10.1007/978-3-642-05197-5_11openalex-snapshot
A Memory Efficient Network Encryption Scheme
inferred← citeshttps://doi.org/10.1007/978-3-642-23951-9_1openalex-snapshot
An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
inferred← citeshttps://doi.org/10.1007/978-3-642-23951-9_33openalex-snapshot
Efficient Hashing Using the AES Instruction Set
inferred← citeshttps://doi.org/10.1007/978-3-642-24669-2_29openalex-snapshot
Fast Software Implementation of AES-CCM on Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-32946-3_22openalex-snapshot
CTL: A Platform-Independent Crypto Tools Library Based on Dataflow Programming Paradigm
inferred← citeshttps://doi.org/10.1007/978-3-642-36140-1_11openalex-snapshot
On Using Instruction-Set Extensions for Minimizing the Hardware-Implementation Costs of Symmetric-Key Algorithms on a Low-Resource Microcontroller
inferred← citeshttps://doi.org/10.1007/s10617-008-9027-xopenalex-snapshot
Embedded systems security—an overview
inferred← citeshttps://doi.org/10.1007/s11042-018-5660-yopenalex-snapshot
One round cipher algorithm for multimedia IoT devices
inferred← citeshttps://doi.org/10.1007/s11042-020-09625-8openalex-snapshot
Speck-R: An ultra light-weight cryptographic scheme for Internet of Things
inferred← citeshttps://doi.org/10.1007/s11265-007-0158-2openalex-snapshot
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
inferred← citeshttps://doi.org/10.1007/s12652-017-0494-4openalex-snapshot
Advanced lightweight encryption algorithms for IoT devices: survey, challenges and solutions
inferred← citeshttps://doi.org/10.1007/s13389-011-0025-8openalex-snapshot
An exploration of mechanisms for dynamic cryptographic instruction set extension
inferred← citeshttps://doi.org/10.1007/s42979-025-04309-2openalex-snapshot
Evaluating the RISCV-EC: A Comparative Analysis of Instruction Efficiency and Power Performance for Edge Computing
inferred← citeshttps://doi.org/10.1016/j.image.2013.08.015openalex-snapshot
Secure computing with the MPEG RVC framework
inferred← citeshttps://doi.org/10.1016/j.jnca.2015.09.001openalex-snapshot
A survey on lightweight block ciphers for low-resource devices: Comparative study and open issues
inferred← citeshttps://doi.org/10.1016/j.jpdc.2011.04.006openalex-snapshot
FPGA implementation and performance evaluation of a high throughput crypto coprocessor
inferred← citeshttps://doi.org/10.1016/j.mejo.2021.105165openalex-snapshot
An energy-efficient crypto-extension design for RISC-V
inferred← citeshttps://doi.org/10.1016/j.procs.2024.10.225openalex-snapshot
Cryptography Performance Analysis in Intel Core i5-12500H and AMD Ryzen 7 5800H Processors: Implications for Secure Computing
inferred← citeshttps://doi.org/10.1109/acsac.2008.10openalex-snapshot
Instruction Set Extensions for Enhancing the Performance of Symmetric-Key Cryptography
inferred← citeshttps://doi.org/10.1109/ainaw.2007.182openalex-snapshot
Fast and Efficient Implementation of AES via Instruction Set Extensions
inferred← citeshttps://doi.org/10.1109/ares.2014.32openalex-snapshot
AES-SEC: Improving Software Obfuscation through Hardware-Assistance
inferred← citeshttps://doi.org/10.1109/asap57973.2023.00034openalex-snapshot
Resource-Constrained Encryption: Extending Ibex with a QARMA Hardware Accelerator
inferred← citeshttps://doi.org/10.1109/cis.2007.103openalex-snapshot
Design of an Instruction for Fast and Efficient S-Box Implementation
inferred← citeshttps://doi.org/10.1109/cis.2007.120openalex-snapshot
Image Encryption Algorithm of Double Scrambling Based on ASCII Code of Matrix Element
inferred← citeshttps://doi.org/10.1109/cis.2007.151openalex-snapshot
A Study on the Method of Attribute Reduction Based on Rough Set under Fuzzy Equivalent Relation
inferred← citeshttps://doi.org/10.1109/csr57506.2023.10224966openalex-snapshot
Area-Delay Efficient Security Scheme for Smart Hospital Systems
inferred← citeshttps://doi.org/10.1109/dtis.2013.6527783openalex-snapshot
Lightweight cipher implementations on embedded processors
inferred← citeshttps://doi.org/10.1109/ebiss.2009.5137980openalex-snapshot
Fast S-Box Substitution Instructions and Their Hardware Implementation for Accelerating Symmetric Cryptographic Processing
inferred← citeshttps://doi.org/10.1109/edssc.2015.7285111openalex-snapshot
FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension
inferred← citeshttps://doi.org/10.1109/gcwcn66157.2025.11448421openalex-snapshot
Extended AES with Custom Configurable Encryption
inferred← citeshttps://doi.org/10.1109/hst.2008.4559060openalex-snapshot
Reassessing the TCG specifications for trusted computing in mobile and embedded systems
inferred← citeshttps://doi.org/10.1109/iccet.2009.248openalex-snapshot
An AES Tightly Coupled Hardware Accelerator in an FPGA-based Embedded Processor Core
inferred← citeshttps://doi.org/10.1109/icecs.2015.7440343openalex-snapshot
Fault tolerant register file design for MIPS AES-crypto microprocessor
inferred← citeshttps://doi.org/10.1109/icis54925.2022.9882453openalex-snapshot
A Trigonometric Function Instruction Set Extension Method Based on RISC-V
inferred← citeshttps://doi.org/10.1109/ipdps.2011.199openalex-snapshot
GALS-Based LPSP: Implementation of a Novel Architecture for Low Power High Performance Security Processors
inferred← citeshttps://doi.org/10.1109/isce.2009.5157053openalex-snapshot
Exploring HW/SW codesign of AES algorithm using custom instructions
inferred← citeshttps://doi.org/10.1109/isqed.2015.7085468openalex-snapshot
Side channel attacks in embedded systems: A tale of hostilities and deterrence
inferred← citeshttps://doi.org/10.1109/issoc.2010.5625557openalex-snapshot
A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography
inferred← citeshttps://doi.org/10.1109/itng.2009.163openalex-snapshot
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip
inferred← citeshttps://doi.org/10.1109/jetcas.2014.2315877openalex-snapshot
A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES
inferred← citeshttps://doi.org/10.1109/jiot.2014.2360217openalex-snapshot
Characterizing the Performance of Security Functions in Mobile Computing Systems
inferred← citeshttps://doi.org/10.1109/jiot.2025.3611318openalex-snapshot
Tree-Feistel Cipher Standard for IoT Communication System
inferred← citeshttps://doi.org/10.1109/les.2012.2234080openalex-snapshot
Softcore Processor Optimization According to Real-Application Requirements
inferred← citeshttps://doi.org/10.1109/mass.2019.00025openalex-snapshot
Falcon — A Flexible Architecture For Accelerating Cryptography
inferred← citeshttps://doi.org/10.1109/pervasive.2015.7087117openalex-snapshot
ISA customization for application specific instruction set processors
inferred← citeshttps://doi.org/10.1109/reconfig.2008.59openalex-snapshot
Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security
inferred← citeshttps://doi.org/10.1109/sasp.2010.5521153openalex-snapshot
Processor accelerator for AES
inferred← citeshttps://doi.org/10.1109/tc.2021.3050515openalex-snapshot
Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading
inferred← citeshttps://doi.org/10.1109/trustcom.2011.138openalex-snapshot
A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2025171openalex-snapshot
Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set Extensions
inferred← citeshttps://doi.org/10.1109/waina.2008.278openalex-snapshot
How to Optimize the Cryptographic Symmetric Primitives on Loongson-2E Microprocessor
inferred← citeshttps://doi.org/10.1109/wcncw.2015.7122526openalex-snapshot
Towards distributing block ciphers computations
inferred← citeshttps://doi.org/10.1115/1.802977.paper114openalex-snapshot
Fastcrypto: Parallel AES Pipelines Extension for General-Purpose Processors
inferred← citeshttps://doi.org/10.1145/1626195.1626233openalex-snapshot
Efficient, secure, and isolated execution of cryptographic algorithms on a cryptographic unit
inferred← citeshttps://doi.org/10.1145/1920261.1920293openalex-snapshot
SCA-resistant embedded processors
inferred← citeshttps://doi.org/10.1145/1958746.1958800openalex-snapshot
Workload characterization of cryptography algorithms for hardware acceleration
inferred← citeshttps://doi.org/10.1145/2501654.2501655openalex-snapshot
Architectures of flexible symmetric key crypto engines—a survey
inferred← citeshttps://doi.org/10.1145/3123939.3124546openalex-snapshot
How secure is your cache against side-channel attacks?
inferred← citeshttps://doi.org/10.1504/ijhpsa.2010.034537openalex-snapshot
Parallel processing for block ciphers on a fault tolerant networked processor array
inferred← citeshttps://doi.org/10.1504/ijhpsa.2010.034541openalex-snapshot
Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform
inferred← citeshttps://doi.org/10.15803/ijnc.2.1_56openalex-snapshot
GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors
inferred← citeshttps://doi.org/10.3233/jcs-2008-16302openalex-snapshot
Accelerated AES implementations via generalized instruction set extensions
inferred← citeshttps://doi.org/10.3390/s19030556openalex-snapshot
CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things
inferred← citeshttps://doi.org/10.3850/9783981537079_1009openalex-snapshot
Instruction Set Extensions for Secure Applications
inferred← citeshttps://doi.org/10.4018/978-1-5225-2845-6.ch013openalex-snapshot
Side-Channel Attacks in the Internet of Things
inferred← citeshttps://doi.org/10.4018/978-1-7998-7705-9.ch091openalex-snapshot
Side-Channel Attacks in the Internet of Things
inferred← citeshttps://doi.org/10.46586/tches.v2021.i1.109-136openalex-snapshot
The design of scalar AES Instruction Set Extensions for RISC-V
inferred← citeshttps://doi.org/10.5121/ijcsit.2014.6603openalex-snapshot
A Design of a Fast Parallel-Pipelined Implementation of AES: Advanced Encryption Standard
inferred← citeshttps://doi.org/10.70675/67a331fdz18adz4343z9fd4zf84619227e12openalex-snapshot
Conception d’un crypto-système reconfigurable pour la radio logicielle sécurisée
inferred← citeshttps://doi.org/10.70675/b38fcc34z2bddz4b1cz953ez08661545dce7openalex-snapshot
Crypto-processor – architecture, programming and evaluation of the security
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.