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Dynamic Dictionary-Based Data Compression for Level-1 Caches
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/s1383-7621(00)00030-8openalex-snapshot
An on-chip cache compression technique to reduce decompression overhead and design complexity
inferredcites →https://doi.org/10.1080/1206212x.2003.11441690openalex-snapshot
Adaptive Methods to Minimize Decompression Overhead for Compressed On-Chip Caches
inferredcites →https://doi.org/10.1109/40.918003openalex-snapshot
Pinnacle: IBM MXT in a memory controller chip
inferredcites →https://doi.org/10.1109/92.736129openalex-snapshot
Working-zone encoding for reducing the energy in microprocessor address buses
inferredcites →https://doi.org/10.1109/hpca.1995.386552openalex-snapshot
Creating a wider bus using caching techniques
inferredcites →https://doi.org/10.1109/hpca.2005.4openalex-snapshot
A Unified Compressed Memory Hierarchy
inferredcites →https://doi.org/10.1109/iccd.2005.94openalex-snapshot
Restrictive compression techniques to increase level 1 cache capacity
inferredcites →https://doi.org/10.1109/iccd11805.2006openalex-snapshot
2006 International Conference on Computer Design
inferredcites →https://doi.org/10.1109/isca.2004.1310776openalex-snapshot
Adaptive cache compression for high-performance processors
inferredcites →https://doi.org/10.1109/isca.2005.6openalex-snapshot
A robust main-memory compression scheme
inferredcites →https://doi.org/10.1109/lpe.2005.195539openalex-snapshot
A tunable bus encoder for off-chip data buses
inferredcites →https://doi.org/10.1109/micro.1997.645817openalex-snapshot
Can program profiling support value prediction?
inferredcites →https://doi.org/10.1109/micro.2002.1176262openalex-snapshot
Power protocol: reducing power dissipation on off-chip data buses
inferredcites →https://doi.org/10.1145/1013948.1013953openalex-snapshot
Frequent value encoding for low power data buses
inferredcites →https://doi.org/10.1145/1028176.1006719openalex-snapshot
Adaptive Cache Compression for High-Performance Processors
inferredcites →https://doi.org/10.1145/1080695.1069978openalex-snapshot
A Robust Main-Memory Compression Scheme
inferredcites →https://doi.org/10.1145/237090.237173openalex-snapshot
Value locality and load value prediction
inferredcites →https://doi.org/10.1145/313817.313860openalex-snapshot
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
inferredcites →https://doi.org/10.1145/356989.357003openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/360128.360150openalex-snapshot
Dynamic zero compression for cache energy reduction
inferredcites →https://doi.org/10.1145/360128.360154openalex-snapshot
Frequent value compression in data caches
inferredcites →https://doi.org/10.1145/378993.379235openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/383082.383086openalex-snapshot
L1 data cache decomposition for energy efficiency
inferredcites →https://doi.org/10.1145/581888.581894openalex-snapshot
Frequent value locality and its applications
inferredcites →https://doi.org/10.1145/951710.951745openalex-snapshot
Power efficient encoding techniques for off-chip data buses
inferredcites →https://doi.org/10.5555/266800.266826openalex-snapshot
Can program profiling support value prediction
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00080openalex-snapshot
Enterprise-Class Cache Compression Design
inferred← citeshttps://doi.org/10.1109/iccd.2017.61openalex-snapshot
Dual Dictionary Compression for the Last Level Cache
inferred← citeshttps://doi.org/10.1109/tpds.2015.2435788openalex-snapshot
A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems
inferred← citeshttps://doi.org/10.1145/1534530.1534536openalex-snapshot
Energy and performance evaluation of lossless file data compression on server systems
inferred← citeshttps://doi.org/10.1145/3445814.3446722openalex-snapshot
BCD deduplication: effective memory compression using partial cache-line deduplication
inferred← citeshttps://doi.org/10.17760/d20316358openalex-snapshot
Exploring compression in the GPU memory hierarchy for graphics and compute
inferred← citeshttps://doi.org/10.2200/s00119ed1v01y200805cac004openalex-snapshot
Computer Architecture Techniques for Power-Efficiency
inferred← citeshttps://doi.org/10.3745/kipsta.2008.15-a.5.269openalex-snapshot
Implementation of A Low-Power Embedded System via Scratch-pad Memory Compression
inferred← citeshttps://doi.org/10.70675/ff9a8713ze4f9z421ez8b99zdfef9781d066openalex-snapshot
Towards compression at all levels in the memory hierarchy
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