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Understanding Cache Compression

https://doi.org/10.1145/3457207
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/11574859_3openalex-snapshot
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors
inferredcites →https://doi.org/10.1007/11682127_9openalex-snapshot
Dynamic Dictionary-Based Data Compression for Level-1 Caches
inferredcites →https://doi.org/10.1007/3-540-44687-7_65openalex-snapshot
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor
inferredcites →https://doi.org/10.1007/3-540-45661-9_21openalex-snapshot
Compression and Information Leakage of Plaintext
inferredcites →https://doi.org/10.1007/978-3-540-30566-8_109openalex-snapshot
A Space-Efficient On-Chip Compressed Cache Organization for High Performance Computing
inferredcites →https://doi.org/10.1007/978-3-540-72685-2_14openalex-snapshot
A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching
inferredcites →https://doi.org/10.1016/j.jksuci.2018.05.006openalex-snapshot
A survey on data compression techniques: From the perspective of data quality, coding schemes, data type and applications
inferredcites →https://doi.org/10.1016/s1383-7621(00)00030-8openalex-snapshot
An on-chip cache compression technique to reduce decompression overhead and design complexity
inferredcites →https://doi.org/10.1049/ip-cdt:19981797openalex-snapshot
Empirical study of memory-data: Characteristics and compressibility
inferredcites →https://doi.org/10.1109/40.918003openalex-snapshot
Pinnacle: IBM MXT in a memory controller chip
inferredcites →https://doi.org/10.1109/dcc.2010.42openalex-snapshot
gFPC: A Self-Tuning Compression Algorithm
inferredcites →https://doi.org/10.1109/eurmic.1996.546466openalex-snapshot
Design and performance of a main memory hardware data compressor
inferredcites →https://doi.org/10.1109/eurmic.2000.874391openalex-snapshot
Proceedings Of The 26 Th Euromicro Conference
inferredcites →https://doi.org/10.1109/hpca.2012.6169027openalex-snapshot
Improving write operations in MLC phase change memory
inferredcites →https://doi.org/10.1109/hpca.2014.6835972openalex-snapshot
MemZip: Exploring unconventional benefits from memory compression
inferredcites →https://doi.org/10.1109/hpca.2018.00028openalex-snapshot
LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUs
inferredcites →https://doi.org/10.1109/iccd.2001.954993openalex-snapshot
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
inferredcites →https://doi.org/10.1109/iccd.2013.6657041openalex-snapshot
Data compression for thermal mitigation in the Hybrid Memory Cube
inferredcites →https://doi.org/10.1109/iccd.2013.6657054openalex-snapshot
Free ECC: An efficient error protection for compressed last-level caches
inferredcites →https://doi.org/10.1109/iccd.2015.7357098openalex-snapshot
SCP: Synergistic cache compression and prefetching
inferredcites →https://doi.org/10.1109/isca.1995.524577openalex-snapshot
CAT - caching address tags - a technique for reducing area cost of on-chip caches
inferredcites →https://doi.org/10.1109/isca.2005.6openalex-snapshot
A robust main-memory compression scheme
inferredcites →https://doi.org/10.1109/isca.2016.36openalex-snapshot
Base-Victim Compression: An Opportunistic Cache Compression Architecture
inferredcites →https://doi.org/10.1109/jrproc.1952.273898openalex-snapshot
A Method for the Construction of Minimum-Redundancy Codes
inferredcites →https://doi.org/10.1109/l-ca.2012.31openalex-snapshot
A Case for a Value-Aware Cache
inferredcites →https://doi.org/10.1109/mc.1984.1659158openalex-snapshot
A Technique for High-Performance Data Compression
inferredcites →https://doi.org/10.1109/micro.1996openalex-snapshot
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
inferredcites →https://doi.org/10.1109/micro.2016.7783704openalex-snapshot
Dictionary sharing: An efficient cache compression scheme for compressed caches
inferredcites →https://doi.org/10.1109/micro.2018.00025openalex-snapshot
Rethinking the Memory Hierarchy for Modern Languages
inferredcites →https://doi.org/10.1109/micro.2018.00033openalex-snapshot
CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores
inferredcites →https://doi.org/10.1109/mm.2010.31openalex-snapshot
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
inferredcites →https://doi.org/10.1109/padsw.2018.8644558openalex-snapshot
Data Locality Exploitation in Cache Compression
inferredcites →https://doi.org/10.1109/tc.2008.28openalex-snapshot
Memory-Link Compression Schemes: A Value Locality Perspective
inferredcites →https://doi.org/10.1109/tc.2015.2479585openalex-snapshot
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage
inferredcites →https://doi.org/10.1109/tc.2015.2493533openalex-snapshot
PBC: Prefetched Blocks Compaction
inferredcites →https://doi.org/10.1109/tcad.2008.917563openalex-snapshot
Bitmask-Based Code Compression for Embedded Systems
inferredcites →https://doi.org/10.1109/tit.1977.1055714openalex-snapshot
A universal algorithm for sequential data compression
inferredcites →https://doi.org/10.1109/tit.1978.1055934openalex-snapshot
Compression of individual sequences via variable-rate coding
inferredcites →https://doi.org/10.1109/tpds.2015.2435788openalex-snapshot
A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems
inferredcites →https://doi.org/10.1109/tvcg.2006.143openalex-snapshot
Fast and Efficient Compression of Floating-Point Data
inferredcites →https://doi.org/10.1109/tvlsi.2009.2020989openalex-snapshot
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
inferredcites →https://doi.org/10.1145/1013948.1013953openalex-snapshot
Frequent value encoding for low power data buses
inferredcites →https://doi.org/10.1145/1028176.1006719openalex-snapshot
Adaptive Cache Compression for High-Performance Processors
inferredcites →https://doi.org/10.1145/1274971.1274999openalex-snapshot
Compression in cache design
inferredcites →https://doi.org/10.1145/1542275.1542288openalex-snapshot
Zero-content augmented caches
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/165123.165153openalex-snapshot
Column-associative caches
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/192007.192072openalex-snapshot
Decoupled sectored caches
inferredcites →https://doi.org/10.1145/2155620.2155670openalex-snapshot
Residue cache
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/223982openalex-snapshot
Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95
inferredcites →https://doi.org/10.1145/2370816.2370870openalex-snapshot
Base-delta-immediate compression
inferredcites →https://doi.org/10.1145/2540708.2540715openalex-snapshot
Decoupled compressed cache
inferredcites →https://doi.org/10.1145/2540708.2540724openalex-snapshot
Linearly compressed pages
inferredcites →https://doi.org/10.1145/2540708.2540735openalex-snapshot
The reuse cache
inferredcites →https://doi.org/10.1145/258916.258947openalex-snapshot
Code compression
inferredcites →https://doi.org/10.1145/2597652.2597655openalex-snapshot
Last-level cache deduplication
inferredcites →https://doi.org/10.1145/2678373.2665696openalex-snapshot
SC2
inferredcites →https://doi.org/10.1145/2749469.2750377openalex-snapshot
COP
inferredcites →https://doi.org/10.1145/2807591.2807659openalex-snapshot
Frugal ECC
inferredcites →https://doi.org/10.1145/2830772.2830790openalex-snapshot
Doppelgänger
inferredcites →https://doi.org/10.1145/2830772.2830823openalex-snapshot
HyComp
inferredcites →https://doi.org/10.1145/2830772.2830828openalex-snapshot
MORC
inferredcites →https://doi.org/10.1145/2893356openalex-snapshot
A Survey of Techniques for Approximate Computing
inferredcites →https://doi.org/10.1145/2976740openalex-snapshot
Yet Another Compressed Cache
inferredcites →https://doi.org/10.1145/2999538openalex-snapshot
HoPE
inferredcites →https://doi.org/10.1145/3007787.3001178openalex-snapshot
Neurocube
inferredcites →https://doi.org/10.1145/30350openalex-snapshot
Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87
inferredcites →https://doi.org/10.1145/3079856.3080243openalex-snapshot
DICE
inferredcites →https://doi.org/10.1145/322344.322346openalex-snapshot
Data compression via textual substitution
inferredcites →https://doi.org/10.1145/3240302.3240304openalex-snapshot
Cocoa
inferredcites →https://doi.org/10.1145/3240302.3240429openalex-snapshot
Opportunistic compression for direct-mapped DRAM caches
inferredcites →https://doi.org/10.1145/3243176.3243178openalex-snapshot
Synergistic cache layout for reuse and compression
inferredcites →https://doi.org/10.1145/3297858.3304006openalex-snapshot
Compress Objects, Not Cache Lines
inferredcites →https://doi.org/10.1145/3352460.3358281openalex-snapshot
Touché
inferredcites →https://doi.org/10.1145/3373376.3378453openalex-snapshot
Safecracker: Leaking Secrets through Compressed Caches
inferredcites →https://doi.org/10.1145/3373376.3378518openalex-snapshot
Thesaurus
inferredcites →https://doi.org/10.1145/339647.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/356887.356892openalex-snapshot
Cache Memories
inferredcites →https://doi.org/10.1145/360128.360150openalex-snapshot
Dynamic zero compression for cache energy reduction
inferredcites →https://doi.org/10.1145/360128.360154openalex-snapshot
Frequent value compression in data caches
inferredcites →https://doi.org/10.1145/368122.368872openalex-snapshot
Effective algorithms for cache-level compression
inferredcites →https://doi.org/10.1145/378993.379235openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/937503.937504openalex-snapshot
Survey of code-size reduction methods
inferredcites →https://doi.org/10.1147/rd.282.0124openalex-snapshot
Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review
inferredcites →https://doi.org/10.1147/rd.452.0271openalex-snapshot
IBM Memory Expansion Technology (MXT)
inferredcites →https://doi.org/10.2200/s00683ed1v01y201511cac036openalex-snapshot
A Primer on Compression in the Memory Hierarchy
inferredcites →https://doi.org/10.23919/date.2018.8342274openalex-snapshot
DFPC: A dynamic frequent pattern compression scheme in NVM-based main memory
inferredcites →https://doi.org/10.5555/3195638.3195690openalex-snapshot
The bunker cache for spatio-value approximation
inferredcites →https://doi.org/10.7551/mitpress/3917.003.0012openalex-snapshot
Content-Addressable Memory

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.compeleceng.2024.109106openalex-snapshot
A novel approximate cache block compressor for error-resilient image data
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00084openalex-snapshot
Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00080openalex-snapshot
Enterprise-Class Cache Compression Design
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00118openalex-snapshot
Ariadne: A Hotness-Aware and Size-Adaptive Compressed Swap Technique for Fast Application Relaunch and Reduced CPU Usage on Mobile Devices
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408535openalex-snapshot
Intermittence-Aware Cache Compression
inferred← citeshttps://doi.org/10.1109/iccd53106.2021.00075openalex-snapshot
Conciliating Speed and Efficiency on Cache Compressors
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00084openalex-snapshot
GPU.zip: On the Side-Channel Implications of Hardware-Based Graphical Data Compression
inferred← citeshttps://doi.org/10.1109/spices62143.2024.10779893openalex-snapshot
A Comprehensive Evaluation of Packet Compression Techniques for NoC
inferred← citeshttps://doi.org/10.1145/3613424.3623784openalex-snapshot
MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
inferred← citeshttps://doi.org/10.1145/3689334openalex-snapshot
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories
inferred← citeshttps://doi.org/10.1145/3721286openalex-snapshot
TSN Cache: Exploiting Data Localities in Graph Computing Applications
inferred← citeshttps://doi.org/10.1145/3771285openalex-snapshot
Object-Aware Memory Compression for Smartphones
inferred← citeshttps://doi.org/10.1145/3830340.3830349openalex-snapshot
Efficient Compression for Data Storage: Detect Early, Prune Deep in Dictionary-Based Algorithms
inferred← citeshttps://doi.org/10.15622/ia.23.3.8openalex-snapshot
Hardware Compression Method for On-Chip and Interprocessor Networks with Wide Channels and Wormhole Flow Control Policy
inferred← citeshttps://doi.org/10.20537/2076-7633-2023-15-3-639-656openalex-snapshot
Reducing miss rate in a non-inclusive cache with inclusive directory of a chip multiprocessor
inferred← citeshttps://doi.org/10.70675/ff9a8713ze4f9z421ez8b99zdfef9781d066openalex-snapshot
Towards compression at all levels in the memory hierarchy
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