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Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination

https://doi.org/10.1007/11859802_6
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4419-8987-1openalex-snapshot
High Performance Memory Systems
inferredcites →https://doi.org/10.1007/978-1-4419-8987-1_4openalex-snapshot
Timestamp-Based Selective Cache Allocation
inferredcites →https://doi.org/10.1016/j.micpro.2004.03.019openalex-snapshot
A cache block reuse prediction scheme
inferredcites →https://doi.org/10.1109/12.817393openalex-snapshot
Run-time cache bypassing
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/cgo.2004.1281683openalex-snapshot
Static identification of delinquent loads
inferredcites →https://doi.org/10.1109/hicss.1989.47168openalex-snapshot
Improving cache performance by selective cache bypass
inferredcites →https://doi.org/10.1109/hpca.2000.824338openalex-snapshot
Modified LRU policies for improving second-level cache behavior
inferredcites →https://doi.org/10.1109/hpca.2003.1183548openalex-snapshot
Just say no: benefits of early cache miss determination
inferredcites →https://doi.org/10.1109/iccd.1997.628916openalex-snapshot
Design and performance evaluation of a cache assist to implement selective caching
inferredcites →https://doi.org/10.1109/micro.1993.282750openalex-snapshot
Predictability of load/store instruction latencies
inferredcites →https://doi.org/10.1109/micro.1995.476816openalex-snapshot
A modified approach to data cache management
inferredcites →https://doi.org/10.1145/139669.139727openalex-snapshot
Cache replacement with dynamic exclusion
inferredcites →https://doi.org/10.1145/166955.166974openalex-snapshot
Efficient simulation of caches under optimal replacement with applications to miss characterization
inferredcites →https://doi.org/10.1145/277830.277941openalex-snapshot
Utilizing reuse information in data cache management
inferredcites →https://doi.org/10.1145/977091.977117openalex-snapshot
Self-correcting LRU replacement policies
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/225160.225177openalex-snapshot
A modified approach to data cache management
inferredcites →https://doi.org/10.5555/255235.255275openalex-snapshot
Predictability of load/store instruction latencies
inferredcites →https://doi.org/10.5555/977395.977676openalex-snapshot
Static identification of delinquent loads

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-540-74309-5_11openalex-snapshot
Exploiting Single-Usage for Effective Memory Management
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.05.005openalex-snapshot
A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines
inferred← citeshttps://doi.org/10.1109/aeect.2013.6716445openalex-snapshot
SCIP: Selective cache insertion and bypassing to improve the performance of last-level caches
inferred← citeshttps://doi.org/10.1109/ipdps.2013.16openalex-snapshot
Adaptive Cache Bypassing for Inclusive Last Level Caches
inferred← citeshttps://doi.org/10.1109/isca.2018.00050openalex-snapshot
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00145openalex-snapshot
Bumper: Hinting Instruction Usefulness for Robust Unified Caches
inferred← citeshttps://doi.org/10.1109/micro.2008.4771796openalex-snapshot
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00023openalex-snapshot
CHiRP: Control-Flow History Reuse Prediction
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00015openalex-snapshot
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
inferred← citeshttps://doi.org/10.1109/rtss.2009.34openalex-snapshot
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
inferred← citeshttps://doi.org/10.1109/sbac-pad55451.2022.00017openalex-snapshot
Dynamic Set Stealing to Improve Cache Performance
inferred← citeshttps://doi.org/10.1109/tc.2007.70816openalex-snapshot
Counter-Based Cache Replacement and Bypassing Algorithms
inferred← citeshttps://doi.org/10.1109/tc.2016.2529621openalex-snapshot
Statistical Cache Bypassing for Non-Volatile Memory
inferred← citeshttps://doi.org/10.1142/s0218126621502923openalex-snapshot
LPE: Locality-Based Dead Prediction in Exclusive TLB for Large Coverage
inferred← citeshttps://doi.org/10.1145/1166133.1166139openalex-snapshot
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
inferred← citeshttps://doi.org/10.1145/1327312.1327320openalex-snapshot
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
inferred← citeshttps://doi.org/10.1145/2184751.2184803openalex-snapshot
Code-based cache partitioning for improving hardware cache performance
inferred← citeshttps://doi.org/10.1145/2627369.2627611openalex-snapshot
SBAC
inferred← citeshttps://doi.org/10.1145/2811411.2811512openalex-snapshot
Bypassing method for STT-RAM based inclusive last-level cache
inferred← citeshttps://doi.org/10.1145/2971331.2971334openalex-snapshot
Probabilistic Directed Writebacks for Exclusive Caches
inferred← citeshttps://doi.org/10.1145/3620666.3651353openalex-snapshot
GMT: GPU Orchestrated Memory Tiering for the Big Data Era
inferred← citeshttps://doi.org/10.1145/3650200.3656604openalex-snapshot
NUCAlloc: Fine-Grained Block Placement in Hashed Last-Level NUCA Caches
inferred← citeshttps://doi.org/10.1145/3695794.3695803openalex-snapshot
PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC
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