On the public citation graph
Adaptive Cache Bypassing for Inclusive Last Level Caches
0 signed · 65 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11859802_6openalex-snapshot
Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination
inferredcites →https://doi.org/10.1007/978-1-4419-8987-1_4openalex-snapshot
Timestamp-Based Selective Cache Allocation
inferredcites →https://doi.org/10.1109/2.268884openalex-snapshot
Caching strategies to improve disk system performance
inferredcites →https://doi.org/10.1109/hicss.1989.47168openalex-snapshot
Improving cache performance by selective cache bypass
inferredcites →https://doi.org/10.1109/iccd.2010.5647608openalex-snapshot
Insertion policy selection using Decision Tree Analysis
inferredcites →https://doi.org/10.1109/icpp.1996.537156openalex-snapshot
Reducing conflicts in direct-mapped caches with a temporality-based design
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1109/micro.1995.476816openalex-snapshot
A modified approach to data cache management
inferredcites →https://doi.org/10.1109/micro.2010.52openalex-snapshot
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies
inferredcites →https://doi.org/10.1109/tc.2007.70816openalex-snapshot
Counter-Based Cache Replacement and Bypassing Algorithms
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/2000064.2000075openalex-snapshot
Bypass and insertion algorithms for exclusive last-level caches
inferredcites →https://doi.org/10.1145/2370816.2370862openalex-snapshot
Optimal bypass monitor for high performance last-level caches
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/225160.225177openalex-snapshot
A modified approach to data cache management
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-22677-9_15openalex-snapshot
GEM: Execution-Aware Cache Management for Graph Analytics
inferred← citeshttps://doi.org/10.1007/978-3-319-78890-6_28openalex-snapshot
Runtime Adaptive Cache for the LEON3 Processor
inferred← citeshttps://doi.org/10.1007/978-81-322-2731-1_4openalex-snapshot
A Pragmatic Delineation on Cache Bypass Algorithm in Last-Level Cache (LLC)
inferred← citeshttps://doi.org/10.1007/s10586-015-0470-8openalex-snapshot
A novel memory management technique for cloud client devices
inferred← citeshttps://doi.org/10.1007/s11390-023-2939-xopenalex-snapshot
Skyway: Accelerate Graph Applications with a Dual-Path Architecture and Fine-Grained Data Management
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.005openalex-snapshot
ReD: A reuse detector for content selection in exclusive shared last-level caches
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.11.005openalex-snapshot
Victim retention for reducing cache misses in tiled chip multiprocessors
inferred← citeshttps://doi.org/10.1049/iet-cdt.2014.0150openalex-snapshot
SkipCache: application aware cache management for chip multi‐processors
inferred← citeshttps://doi.org/10.1109/access.2020.2981540openalex-snapshot
Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM
inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.1109/aeect.2013.6716445openalex-snapshot
SCIP: Selective cache insertion and bypassing to improve the performance of last-level caches
inferred← citeshttps://doi.org/10.1109/hpca.2017.25openalex-snapshot
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071033openalex-snapshot
ACIC: Admission-Controlled Instruction Cache
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753269openalex-snapshot
Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement
inferred← citeshttps://doi.org/10.1109/icitcs.2014.7021713openalex-snapshot
A Novel Prefetch Technique for High Performance Embedded System
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00015openalex-snapshot
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions
inferred← citeshttps://doi.org/10.1109/ispa.2014.30openalex-snapshot
Future Trends on Adaptive Processing Systems
inferred← citeshttps://doi.org/10.1109/pact.2015.38openalex-snapshot
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
inferred← citeshttps://doi.org/10.1109/samos.2016.7818332openalex-snapshot
A bypass first policy for energy-efficient last level caches
inferred← citeshttps://doi.org/10.1109/sbac-pad55451.2022.00018openalex-snapshot
Avoiding Unnecessary Caching with History-Based Preemptive Bypassing
inferred← citeshttps://doi.org/10.1109/sbac-padw.2014.14openalex-snapshot
RACB: Resource Aware Cache Bypass on GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012789openalex-snapshot
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities
inferred← citeshttps://doi.org/10.1109/tetc.2017.2653813openalex-snapshot
Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM
inferred← citeshttps://doi.org/10.1109/tpds.2023.3297595openalex-snapshot
A Survey of Memory-Centric Energy Efficient Computer Architecture
inferred← citeshttps://doi.org/10.1142/s0218126621502923openalex-snapshot
LPE: Locality-Based Dead Prediction in Exclusive TLB for Large Coverage
inferred← citeshttps://doi.org/10.1145/2633046openalex-snapshot
Preventing STT-RAM Last-Level Caches from Port Obstruction
inferred← citeshttps://doi.org/10.1145/2811411.2811512openalex-snapshot
Bypassing method for STT-RAM based inclusive last-level cache
inferred← citeshttps://doi.org/10.1145/2971331.2971334openalex-snapshot
Probabilistic Directed Writebacks for Exclusive Caches
inferred← citeshttps://doi.org/10.1145/3075564.3075591openalex-snapshot
Using Personality Metrics to Improve Cache Interference Management in Multicore Processors
inferred← citeshttps://doi.org/10.1145/3079079.3079089openalex-snapshot
Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures
inferred← citeshttps://doi.org/10.1184/r1/6723512openalex-snapshot
Techniques for Shared Resource Management in Systems with Throughput Processors
inferred← citeshttps://doi.org/10.1587/elex.14.20170324openalex-snapshot
A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs
inferred← citeshttps://doi.org/10.1587/transcom.2020ebp3017openalex-snapshot
Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM
inferred← citeshttps://doi.org/10.20319/pijtel.2024.81.3546openalex-snapshot
PERFORMANCE ANALYSIS OF PRIORITY BASED MEMORY BALANCING TECHNIQUES IN IOT USING MACHINE LEARNING
inferred← citeshttps://doi.org/10.3390/electronics11020240openalex-snapshot
Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches
inferred← citeshttps://doi.org/10.3390/jlpea6020005openalex-snapshot
A Survey of Cache Bypassing Techniques
inferred← citeshttps://doi.org/10.3929/ethz-b-000519275openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11038openalex-snapshot
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
inferred← citeshttps://doi.org/10.5753/sbesc_estendido.2019.8643openalex-snapshot
Acelerando requisições de prováveis cache misses com requisições em paralelo cache/DRAM
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.