On the public citation graph
Ultra Low-Power Electronics and Design
0 signed · 150 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-45716-x_17openalex-snapshot
Robust SAT-Based Search Algorithm for Leakage Power Reduction
inferredcites →https://doi.org/10.1007/978-0-585-29603-6_17openalex-snapshot
Scheduling for Reduced CPU Energy
inferredcites →https://doi.org/10.1007/978-1-4419-9292-5_6openalex-snapshot
Energy Management of Virtual Memory on Diskless Devices
inferredcites →https://doi.org/10.1007/978-3-540-39762-5_43openalex-snapshot
Remote Power Control of Wireless Network Interfaces
inferredcites →https://doi.org/10.1016/b978-0-12-397888-2.00008-0openalex-snapshot
A fourth generation of LCD backlight technology
inferredcites →https://doi.org/10.1023/a:1019051330479openalex-snapshot
The Network RamDisk: Using remote memory on heterogeneous NOWs
inferredcites →https://doi.org/10.1023/b:daem.0000003962.54165.5copenalex-snapshot
Performance Analysis of Arbitration Policies for SoC Communication Architectures
inferredcites →https://doi.org/10.1049/ip-cdt:20030978openalex-snapshot
Low-power system-on-chip architecture for wireless LANs
inferredcites →https://doi.org/10.1109/16.477590openalex-snapshot
Dynamic characterization of a-Si TFT-LCD pixels
inferredcites →https://doi.org/10.1109/16.853042openalex-snapshot
A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/30.793577openalex-snapshot
Chip-set for video display of multimedia information
inferredcites →https://doi.org/10.1109/4.400426openalex-snapshot
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
inferredcites →https://doi.org/10.1109/4.509853openalex-snapshot
Power dissipation analysis and optimization of deep submicron CMOS digital circuits
inferredcites →https://doi.org/10.1109/4.585288openalex-snapshot
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
inferredcites →https://doi.org/10.1109/43.766723openalex-snapshot
Models and algorithms for bounds on leakage in CMOS circuits
inferredcites →https://doi.org/10.1109/43.992764openalex-snapshot
Architectural energy optimization by bus splitting
inferredcites →https://doi.org/10.1109/5.929646openalex-snapshot
High-performance interconnects: an integration overview
inferredcites →https://doi.org/10.1109/71.219761openalex-snapshot
Deadlock-free adaptive routing in multicomputer networks using virtual channels
inferredcites →https://doi.org/10.1109/92.863617openalex-snapshot
Toward achieving energy efficiency in presence of deep submicron noise
inferredcites →https://doi.org/10.1109/aero.2002.1036909openalex-snapshot
Low-power reconfigurable processor
inferredcites →https://doi.org/10.1109/cicc.1997.606670openalex-snapshot
A gate-level leakage power reduction method for ultra-low-power CMOS circuits
inferredcites →https://doi.org/10.1109/cicc.2000.852696openalex-snapshot
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration
inferredcites →https://doi.org/10.1109/cicc.2003.1249411openalex-snapshot
A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability
inferredcites →https://doi.org/10.1109/delta.2002.994599openalex-snapshot
Interconnect IP node for future system-on-chip designs
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/iccd.1997.628902openalex-snapshot
Power constrained design of multiprocessor interconnection networks
inferredcites →https://doi.org/10.1109/iccd.1999.808553openalex-snapshot
System-on-a-chip bus architecture for embedded applications
inferredcites →https://doi.org/10.1109/iccd.2012.6378615openalex-snapshot
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs
inferredcites →https://doi.org/10.1109/icecs.2003.1301862openalex-snapshot
Perceptually optimised sign language video coding
inferredcites →https://doi.org/10.1109/icip.2003.1247192openalex-snapshot
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
inferredcites →https://doi.org/10.1109/icvd.1997.568088openalex-snapshot
Behavioral array mapping into multiport memories targeting low power
inferredcites →https://doi.org/10.1109/icvd.2001.902636openalex-snapshot
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures
inferredcites →https://doi.org/10.1109/ipdps.2004.1303115openalex-snapshot
Integrated modeling and generation of a reconfigurable network-on-chip
inferredcites →https://doi.org/10.1109/ipps.1998.669928openalex-snapshot
Code transformations for low power caching in embedded multimedia processors
inferredcites →https://doi.org/10.1109/isqed.2003.1194710openalex-snapshot
Design techniques for gate-leakage reduction in CMOS circuits
inferredcites →https://doi.org/10.1109/isscc.2000.839694openalex-snapshot
A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications
inferredcites →https://doi.org/10.1109/isscc.2003.1234390openalex-snapshot
An 800MHz star-connected on-chip network for application to systems on a chip
inferredcites →https://doi.org/10.1109/isscc.2004.1332639openalex-snapshot
A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform
inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot
A network on chip architecture and design methodology
inferredcites →https://doi.org/10.1109/iwrsp.2003.1207044openalex-snapshot
Cache configuration exploration on prototyping platforms
inferredcites →https://doi.org/10.1109/iwv.1999.760456openalex-snapshot
Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs
inferredcites →https://doi.org/10.1109/sips.2000.886751openalex-snapshot
Low power multi-module, multi-port memory design for embedded systems
inferredcites →https://doi.org/10.1109/tcad.2002.804107openalex-snapshot
Platune: a tuning framework for system-on-a-chip platforms
inferredcites →https://doi.org/10.1109/vlsit.2000.852781openalex-snapshot
Limits of gate-oxide scaling in nano-transistors
inferredcites →https://doi.org/10.1145/1027084.1027086openalex-snapshot
Cache optimization for embedded processor cores
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/197405.197406openalex-snapshot
Compiler transformations for high-performance computing
inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot
The case for a single-chip multiprocessor
inferredcites →https://doi.org/10.1145/266021.266182openalex-snapshot
Transistor sizing issues and tool for multi-threshold CMOS technology
inferredcites →https://doi.org/10.1145/277044.277179openalex-snapshot
Design and optimization of low voltage high performance dual threshold CMOS circuits
inferredcites →https://doi.org/10.1145/280756.280917openalex-snapshot
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
inferredcites →https://doi.org/10.1145/288548.289076openalex-snapshot
Static power optimization of deep submicron CMOS circuits for dual VT technology
inferredcites →https://doi.org/10.1145/344166.344610openalex-snapshot
A low power unified cache architecture providing power and performance flexibility (poster session)
inferredcites →https://doi.org/10.1145/378239.378404openalex-snapshot
A quick safari through the reconfiguration jungle
inferredcites →https://doi.org/10.1145/378239.379045openalex-snapshot
Addressing the system-on-a-chip interconnect woes through communication-based design
inferredcites →https://doi.org/10.1145/378239.379047openalex-snapshot
On-chip communication architecture for OC-768 network processors
inferredcites →https://doi.org/10.1145/505348.505363openalex-snapshot
Reconfigurable interconnect for next generation systems
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/566408.566425openalex-snapshot
Circuit-level techniques to control gate leakage for sub-100nm CMOS
inferredcites →https://doi.org/10.1145/566408.566440openalex-snapshot
Low-power color TFT LCD display for hand-held embedded systems
inferredcites →https://doi.org/10.1145/581199.581221openalex-snapshot
An adaptive low-power transmission scheme for on-chip networks
inferredcites →https://doi.org/10.1145/581888.581894openalex-snapshot
Frequent value locality and its applications
inferredcites →https://doi.org/10.1145/605459.605461openalex-snapshot
Energy-aware design of embedded memories
inferredcites →https://doi.org/10.1145/774572.774628openalex-snapshot
Standby power optimization via transistor sizing and dual threshold voltage assignment
inferredcites →https://doi.org/10.1145/774789.774804openalex-snapshot
Multi-objective design space exploration using genetic algorithms
inferredcites →https://doi.org/10.1145/775832.775878openalex-snapshot
Analysis and minimization techniques for total leakage considering gate oxide leakage
inferredcites →https://doi.org/10.1145/859618.859635openalex-snapshot
A highly configurable cache architecture for embedded systems
inferredcites →https://doi.org/10.1145/993396.993405openalex-snapshot
A self-tuning cache architecture for embedded systems
inferredcites →https://doi.org/10.5555/320080.320119openalex-snapshot
Selective cache ways: on-demand cache resource allocation
inferredcites →https://doi.org/10.5555/602902.602998openalex-snapshot
Efficient exploration of the SoC communication architecture design space
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/789083.1022785openalex-snapshot
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
inferredcites →https://doi.org/10.5555/789083.1022804openalex-snapshot
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
inferredcites →https://doi.org/10.5555/789083.1022887openalex-snapshot
Library Functions Timing Characterization for Source-Level Analysis
inferredcites →https://doi.org/10.5555/968878.968996openalex-snapshot
Low static-power frequent-value data caches
inferredcites →https://doi.org/10.5555/968878.968997openalex-snapshot
Using a victim buffer in an application-specific memory hierarchy
inferredcites →https://doi.org/10.5555/968878.968998openalex-snapshot
Automatic tuning of two-level caches to embedded applications
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-6193-8_8openalex-snapshot
System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures
inferred← citeshttps://doi.org/10.1007/978-1-4614-8274-1_13openalex-snapshot
Scalable Architecture for All-Optical Wavelength-Routed Networks-on-Chip
inferred← citeshttps://doi.org/10.1007/978-3-319-27392-1_4openalex-snapshot
Energy-Efficient Digital Processing via Approximate Computing
inferred← citeshttps://doi.org/10.1007/s00034-015-0119-0openalex-snapshot
An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques
inferred← citeshttps://doi.org/10.1016/j.ijleo.2017.03.015openalex-snapshot
Reliable communications in optical network-on-chip by use of fault tolerance approaches
inferred← citeshttps://doi.org/10.1016/j.jpdc.2012.02.003openalex-snapshot
Scalable architecture for a contention-free optical network on-chip
inferred← citeshttps://doi.org/10.1016/j.optcom.2006.08.022openalex-snapshot
PDL free plasma enhanced chemical vapor deposition SiC optical waveguides and devices
inferred← citeshttps://doi.org/10.1016/j.optcom.2013.10.033openalex-snapshot
Deposited amorphous silicon-on-insulator technology for nano-photonic integrated circuits
inferred← citeshttps://doi.org/10.1016/j.suscom.2016.01.002openalex-snapshot
Using Genetic Algorithms to optimise dynamic power saving in communication links subject to quality of service requirements
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.07.003openalex-snapshot
Hierarchical opto-electrical on-chip network for future multiprocessor architectures
inferred← citeshttps://doi.org/10.1016/j.vlsi.2006.10.001openalex-snapshot
Predictions of CMOS compatible on-chip optical interconnect
inferred← citeshttps://doi.org/10.1016/j.vlsi.2017.09.010openalex-snapshot
An energy and area efficient 4:2 compressor based on FinFETs
inferred← citeshttps://doi.org/10.1021/acsphotonics.4c01375openalex-snapshot
Direct on-Chip Optical Communication between Nano Optoelectronic Devices
inferred← citeshttps://doi.org/10.1038/nphoton.2008.31openalex-snapshot
High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks
inferred← citeshttps://doi.org/10.1049/iet-cdt.2009.0066openalex-snapshot
Instruction cache tuning for embedded multitasking applications
inferred← citeshttps://doi.org/10.1049/ip-cdt:20045111openalex-snapshot
Low-power RT-level synthesis techniques: a tutorial
inferred← citeshttps://doi.org/10.1049/pbcs018e_ch12openalex-snapshot
Power minimisation techniques at the RT-level and below
inferred← citeshttps://doi.org/10.1080/00207211003646944openalex-snapshot
Novel direct designs for 3-input XOR function for low-power and high-speed applications
inferred← citeshttps://doi.org/10.1080/00207217.2018.1460767openalex-snapshot
Three novel single-stage full swing 3-input XOR
inferred← citeshttps://doi.org/10.1103/physrevb.106.014308openalex-snapshot
Hydrodynamic signatures in thermal transport in devices based on two-dimensional materials: An ab initio study
inferred← citeshttps://doi.org/10.1109/biocas.2011.6107755openalex-snapshot
An ultra low power digital receiver architecture for biomedical applications
inferred← citeshttps://doi.org/10.1109/coniiti48476.2019.8960856openalex-snapshot
Reducing Dynamic Energy in Networks on Chip
inferred← citeshttps://doi.org/10.1109/enics.2008.26openalex-snapshot
Geometry Optimization in Basic CMOS Cells for Improved Power, Leakage, and Noise Performances
inferred← citeshttps://doi.org/10.1109/iccd.2008.4751857openalex-snapshot
Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities
inferred← citeshttps://doi.org/10.1109/idaacs.2019.8924462openalex-snapshot
ADC for Energy Measurement Systems of Microcontroller
inferred← citeshttps://doi.org/10.1109/iemcon.2018.8615094openalex-snapshot
A 20mV Rectifier for Boosting Internet of Natural Things (IoNT)
inferred← citeshttps://doi.org/10.1109/iraniancee.2015.7146428openalex-snapshot
Ultra low-power 7T SRAM cell design based on CMOS
inferred← citeshttps://doi.org/10.1109/jlt.2008.2010462openalex-snapshot
Highly Integrated Optical 4$\,\times\,$4 Crossbar in Silicon-on-Insulator Technology
inferred← citeshttps://doi.org/10.1109/jstqe.2010.2051798openalex-snapshot
Hybrid Silicon Photonics for Optical Interconnects
inferred← citeshttps://doi.org/10.1109/rbme.2014.2346487openalex-snapshot
Feasibility of Energy-Autonomous Wireless Microsensors for Biomedical Applications: Powering and Communication
inferred← citeshttps://doi.org/10.1109/rteict42901.2018.9012235openalex-snapshot
Comprehensive study on the signaling schemes in on chip interconnects
inferred← citeshttps://doi.org/10.1109/test.2011.6139138openalex-snapshot
Investigation into voltage and process variation-aware manufacturing test
inferred← citeshttps://doi.org/10.1109/tvlsi.2006.884151openalex-snapshot
HVS-Aware Dynamic Backlight Scaling in TFT-LCDs
inferred← citeshttps://doi.org/10.1109/vlsisoc.2010.5642624openalex-snapshot
Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/1053355.1053360openalex-snapshot
Predictions of CMOS compatible on-chip optical interconnect
inferred← citeshttps://doi.org/10.1145/1274858.1274869openalex-snapshot
Power macromodeling of MPSoC message passing primitives
inferred← citeshttps://doi.org/10.1145/1297666.1297685openalex-snapshot
A fuel-cell-battery hybrid for portable embedded systems
inferred← citeshttps://doi.org/10.1145/1999946.1999962openalex-snapshot
All-optical wavelength-routed noc based on a novel hierarchical topology
inferred← citeshttps://doi.org/10.1145/3178453openalex-snapshot
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects
inferred← citeshttps://doi.org/10.1145/3472749.3474823openalex-snapshot
MARS: Nano-Power Battery-free Wireless Interfaces for Touch, Swipe and Speech Input
inferred← citeshttps://doi.org/10.1145/3705572openalex-snapshot
Sustainable Interactive Wireless Stickers
inferred← citeshttps://doi.org/10.1145/3705572.3705579openalex-snapshot
Research Approach and Background
inferred← citeshttps://doi.org/10.1145/3705572.3705580openalex-snapshot
Sensing: Thin, Flexible, and Self-powered Acoustic Vibration, Swipe, and Touch Sensors
inferred← citeshttps://doi.org/10.1145/3705572.3705581openalex-snapshot
Communication: No- or Low-power Wireless Stickers Based on AM/FM Backscatter Communication
inferred← citeshttps://doi.org/10.1145/3705572.3705582openalex-snapshot
Feedback: Low Startup Voltage and Low-power Display
inferred← citeshttps://doi.org/10.18372/2310-5461.47.14932openalex-snapshot
METHOD OF ENSURING NOISE RESISTANCE for MEASUREMENT OF MICROCONTROLLERS MEDIUM ENERGY CONSUMPTION
inferred← citeshttps://doi.org/10.3390/jlpea2010001openalex-snapshot
CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
inferred← citeshttps://doi.org/10.4108/eai.24-8-2015.2261118openalex-snapshot
Simulating Power Saver Network Links in MATLAB
inferred← citeshttps://doi.org/10.70675/53bc1f4azc50fz45b9zb94ez3cd6c68b6158openalex-snapshot
Architectural and protocol exploration for 3D optical network-on-chip
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.