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The cache performance and optimizations of blocked algorithms

https://doi.org/10.1145/106972.106981
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/0743-7315(88)90014-7openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1109/mark.1979.8817192openalex-snapshot
Automatic program transformations for virtual memory computers
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/362875.362879openalex-snapshot
Organizing matrices and matrix operations for paged memory systems
inferredcites →https://doi.org/10.1145/77626.79170openalex-snapshot
A set of level 3 basic linear algebra subprograms
inferredcites →https://doi.org/10.1145/800076.802486openalex-snapshot
I/O complexity
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1177/109434208800200103openalex-snapshot
Impact of Hierarchical Memory Systems On Linear Algebra Algorithm Design
inferredcites →https://doi.org/10.56021/9781421407944openalex-snapshot
Matrix Computations

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.1018openalex-snapshot
Is Morton layout competitive for large two‐dimensional arrays yet?
inferred← citeshttps://doi.org/10.1002/cpe.1182openalex-snapshot
Efficient search‐space pruning for integrated fusion and tiling transformations
inferred← citeshttps://doi.org/10.1002/cpe.5003openalex-snapshot
Extending smart containers for data locality‐aware skeleton programming
inferred← citeshttps://doi.org/10.1002/cpe.630openalex-snapshot
A framework for high‐performance matrix multiplication based on hierarchical abstractions, algorithms and optimized low‐level kernels
inferred← citeshttps://doi.org/10.1002/cpe.773openalex-snapshot
The effect of cache models on iterative compilation for combined tiling and unrolling
inferred← citeshttps://doi.org/10.1002/spe.1089openalex-snapshot
POET: a scripting language for applying parameterized source‐to‐source program transformations
inferred← citeshttps://doi.org/10.1006/jagm.1999.1014openalex-snapshot
How to Pack Trees
inferred← citeshttps://doi.org/10.1006/jcss.2001.1756openalex-snapshot
The Combinatorics of Cache Misses during Matrix Multiplication
inferred← citeshttps://doi.org/10.1006/jpdc.1997.1310openalex-snapshot
Communication-Minimal Tiling of Uniform Dependence Loops
inferred← citeshttps://doi.org/10.1006/jpdc.1997.1415openalex-snapshot
Performance of One's Complement Caches
inferred← citeshttps://doi.org/10.1006/jpdc.1998.1456openalex-snapshot
A Comparison of Implementation Strategies for Nonuniform Data-Parallel Computations
inferred← citeshttps://doi.org/10.1006/jpdc.1999.1552openalex-snapshot
A Matrix-Based Approach to Global Locality Optimization
inferred← citeshttps://doi.org/10.1006/jpdc.2000.1639openalex-snapshot
Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed-Memory Machines
inferred← citeshttps://doi.org/10.1007/1-4020-8076-x_9openalex-snapshot
Source-Level Models for Software Power Optimization
inferred← citeshttps://doi.org/10.1007/10704208_29openalex-snapshot
Shared Memory Parallelization of the GROMOS96 Molecular Dynamics Code
inferred← citeshttps://doi.org/10.1007/10722298_5openalex-snapshot
On Code Generation for Multi-generator WITH-Loops in SAC
inferred← citeshttps://doi.org/10.1007/11532378_10openalex-snapshot
JuliusC: A Practical Approach for the Analysis of Divide-and-Conquer Algorithms
inferred← citeshttps://doi.org/10.1007/11532378_12openalex-snapshot
An ILP-Based Approach to Locality Optimization
inferred← citeshttps://doi.org/10.1007/11532378_19openalex-snapshot
Applying Loop Optimizations to Object-Oriented Abstractions Through General Classification of Array Semantics
inferred← citeshttps://doi.org/10.1007/11558958_28openalex-snapshot
A Matrix-Type for Performance–Portability
inferred← citeshttps://doi.org/10.1007/11558958_84openalex-snapshot
Efficient Execution of Scientific Computation on Geographically Distributed Clusters
inferred← citeshttps://doi.org/10.1007/11573036_57openalex-snapshot
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
inferred← citeshttps://doi.org/10.1007/11751649_84openalex-snapshot
Compiler-Optimized Kernels: An Efficient Alternative to Hand-Coded Inner Kernels
inferred← citeshttps://doi.org/10.1007/11752578_128openalex-snapshot
Adapting Linear Algebra Codes to the Memory Hierarchy Using a Hypermatrix Scheme
inferred← citeshttps://doi.org/10.1007/11752578_16openalex-snapshot
A Study on Load Imbalance in Parallel Hypermatrix Multiplication Using OpenMP
inferred← citeshttps://doi.org/10.1007/11846802_36openalex-snapshot
Automatic Memory Optimizations for Improving MPI Derived Datatype Performance
inferred← citeshttps://doi.org/10.1007/11942634_72openalex-snapshot
Combining Measures for Temporal and Spatial Locality
inferred← citeshttps://doi.org/10.1007/3-540-32390-2_19openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-36265-7_61openalex-snapshot
Memory Architectures for Embedded Systems-On-Chip
inferred← citeshttps://doi.org/10.1007/3-540-44520-x_142openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-44570-6_2openalex-snapshot
Software Controlled Reconfigurable On-chip Memory for High Performance Computing
inferred← citeshttps://doi.org/10.1007/3-540-44681-8_37openalex-snapshot
Cache Models for Iterative Compilation
inferred← citeshttps://doi.org/10.1007/3-540-44681-8_38openalex-snapshot
Data Sequence Locality: A Generalization of Temporal Locality
inferred← citeshttps://doi.org/10.1007/3-540-44688-5_3openalex-snapshot
Fractal Matrix Multiplication: A Case Study on Portability of Cache Performance
inferred← citeshttps://doi.org/10.1007/3-540-44691-5_5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-44905-1_30openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-44985-x_36openalex-snapshot
A Blocked All-Pairs Shortest-Paths Algorithm
inferred← citeshttps://doi.org/10.1007/3-540-45307-5_21openalex-snapshot
Towards Automatic Synthesis of High-Performance Codes for Electronic Structure Calculations: Data Locality Optimization
inferred← citeshttps://doi.org/10.1007/3-540-45361-x_14openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45403-9_9openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45545-0_20openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45545-0_22openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45574-4_10openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45591-4_25openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45706-2_37openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45825-5_63openalex-snapshot
Architectures for an Efficient Application Execution in a Collection of HNOWS
inferred← citeshttps://doi.org/10.1007/3-540-45874-3_10openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-47847-7_26openalex-snapshot
Cache Line Impact on 3D PDE Solvers
inferred← citeshttps://doi.org/10.1007/3-540-48311-x_57openalex-snapshot
I/O-Conscious Tiling for Disk-Resident Data Sets
inferred← citeshttps://doi.org/10.1007/3-540-49164-3_13openalex-snapshot
Blocking Techniques in Numerical Software
inferred← citeshttps://doi.org/10.1007/3-540-49164-3_44openalex-snapshot
Reducing Cache Conflicts by a Parametrized Memory Mapping
inferred← citeshttps://doi.org/10.1007/3-540-49372-7_6openalex-snapshot
The Matrix Template Library: A Generic Programming Approach to High Performance Numerical Linear Algebra
inferred← citeshttps://doi.org/10.1007/3-540-49530-4_2openalex-snapshot
Memory System Support for Irregular Applications
inferred← citeshttps://doi.org/10.1007/3-540-55599-4_125openalex-snapshot
Stanford DASH multiprocessor: The hardware and software approach
inferred← citeshttps://doi.org/10.1007/3-540-55599-4_98openalex-snapshot
A new program transformation to minimise communication in distributed memory architectures
inferred← citeshttps://doi.org/10.1007/3-540-55895-0_423openalex-snapshot
An implementation of the BLAS on the i860: A RISC approach to software for RISC devices
inferred← citeshttps://doi.org/10.1007/3-540-55984-1_18openalex-snapshot
Register pipelining: An integrated approach to register allocation for scalar and subscripted variables
inferred← citeshttps://doi.org/10.1007/3-540-56731-3_9openalex-snapshot
Massively parallel computing: Data distribution and communication
inferred← citeshttps://doi.org/10.1007/3-540-56891-3_24openalex-snapshot
Skewed-associative caches
inferred← citeshttps://doi.org/10.1007/3-540-56891-3_3openalex-snapshot
Simulating the data diffusion machine
inferred← citeshttps://doi.org/10.1007/3-540-57840-4_26openalex-snapshot
Increasing memory bandwidth for vector computations
inferred← citeshttps://doi.org/10.1007/3-540-58430-7_3openalex-snapshot
Locality optimizations for parallel machines
inferred← citeshttps://doi.org/10.1007/3-540-60313-1_138openalex-snapshot
Packing trees
inferred← citeshttps://doi.org/10.1007/3-540-61142-8_593openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-61626-8_53openalex-snapshot
A unified transformation technique for multilevel blocking
inferred← citeshttps://doi.org/10.1007/3-540-63138-0_16openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-63138-0_17openalex-snapshot
A support for non-uniform parallel loops and its application to a flame simulation code
inferred← citeshttps://doi.org/10.1007/3-540-63827-x_62openalex-snapshot
The role of abstraction in high-performance computing
inferred← citeshttps://doi.org/10.1007/978-1-4471-3501-2_8openalex-snapshot
A Quantitative Algorithm for Data Locality Optimization
inferred← citeshttps://doi.org/10.1007/978-1-4615-1527-2_11openalex-snapshot
Data Management for Sequential Computer Systems
inferred← citeshttps://doi.org/10.1007/978-1-4615-2315-4_5openalex-snapshot
A Compiler Strategy for Shared Virtual Memories
inferred← citeshttps://doi.org/10.1007/978-1-4757-3337-2_2openalex-snapshot
An Efficient Semi-Hierarchical Array Layout
inferred← citeshttps://doi.org/10.1007/978-1-4757-3337-2_3openalex-snapshot
Impact of Tile-Size Selection for Skewed Tiling
inferred← citeshttps://doi.org/10.1007/978-1-4757-5402-5_3openalex-snapshot
Quantification of Memory Communication
inferred← citeshttps://doi.org/10.1007/978-3-030-69244-5_4openalex-snapshot
Memory Access Optimization of High-Order CFD Stencil Computations on GPU
inferred← citeshttps://doi.org/10.1007/978-3-030-98883-8_2openalex-snapshot
Smart Tiling for Program Optimization and Parallelization
inferred← citeshttps://doi.org/10.1007/978-3-032-23100-0_3openalex-snapshot
Multi-CAKE: Extending CAKE to Higher-Order Tensors
inferred← citeshttps://doi.org/10.1007/978-3-032-29365-7_12openalex-snapshot
AI-Guided DSE of GEMM Kernels for Vision Transformers on FPGA-Based Edge Platforms
inferred← citeshttps://doi.org/10.1007/978-3-319-17353-5_21openalex-snapshot
A Study on the Influence of Caching: Sequences of Dense Linear Algebra Kernels
inferred← citeshttps://doi.org/10.1007/978-3-319-17473-0_20openalex-snapshot
Re-Engineering Compiler Transformations to Outperform Database Query Optimizers
inferred← citeshttps://doi.org/10.1007/978-3-319-28262-6_5openalex-snapshot
A Cache-Optimal Alternative to the Unidirectional Hierarchization Algorithm
inferred← citeshttps://doi.org/10.1007/978-3-319-29778-1_15openalex-snapshot
Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers
inferred← citeshttps://doi.org/10.1007/978-3-319-29778-1_6openalex-snapshot
Interactive Composition of Compiler Optimizations
inferred← citeshttps://doi.org/10.1007/978-3-540-24596-4_44openalex-snapshot
Data Locality Optimization for Synthesis of Efficient Out-of-Core Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-540-30218-6_44openalex-snapshot
Efficient Execution on Long-Distance Geographically Distributed Dedicated Clusters
inferred← citeshttps://doi.org/10.1007/978-3-540-39425-9_28openalex-snapshot
Optimization Parameter Selection by Means of Limited Execution and Genetic Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_12openalex-snapshot
A Comparison of Compiler Tiling Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_18openalex-snapshot
Virtual Cache Line: A New Technique to Improve Cache Exploitation for Recursive Data Structures
inferred← citeshttps://doi.org/10.1007/978-3-540-68111-3_69openalex-snapshot
New Data Structures for Matrices and Specialized Inner Kernels: Low Overhead for High Performance
inferred← citeshttps://doi.org/10.1007/978-3-540-68555-5_3openalex-snapshot
On the Interaction of Tiling and Automatic Parallelization
inferred← citeshttps://doi.org/10.1007/978-3-540-69330-7_15openalex-snapshot
Efficient Search-Space Pruning for Integrated Fusion and Tiling Transformations
inferred← citeshttps://doi.org/10.1007/978-3-540-69330-7_23openalex-snapshot
Using Platform-Specific Performance Counters for Dynamic Compilation
inferred← citeshttps://doi.org/10.1007/978-3-540-69330-7_7openalex-snapshot
Applying Data Copy to Improve Memory Performance of General Array Computations
inferred← citeshttps://doi.org/10.1007/978-3-540-69330-7_9openalex-snapshot
Optimizing Matrix Multiplication with a Classifier Learning System
inferred← citeshttps://doi.org/10.1007/978-3-540-69501-1_23openalex-snapshot
Adaptive Loop Tiling for a Multi-cluster CMP
inferred← citeshttps://doi.org/10.1007/978-3-540-72521-3_6openalex-snapshot
Dependence-Based Code Generation for a CELL Processor
inferred← citeshttps://doi.org/10.1007/978-3-540-75755-9_70openalex-snapshot
Using Non-canonical Array Layouts in Dense Matrix Operations
inferred← citeshttps://doi.org/10.1007/978-3-540-77220-0_13openalex-snapshot
Evaluating ISA Support and Hardware Support for Recursive Data Layouts
inferred← citeshttps://doi.org/10.1007/978-3-540-77704-5_44openalex-snapshot
Empirical Study for Optimization of Power-Performance with On-Chip Memory
inferred← citeshttps://doi.org/10.1007/978-3-540-79409-7_4openalex-snapshot
Modelling the Performance of the Gaussian Chemistry Code on x86 Architectures
inferred← citeshttps://doi.org/10.1007/978-3-642-11467-0_17openalex-snapshot
Implementing P Systems Parallelism by Means of GPUs
inferred← citeshttps://doi.org/10.1007/978-3-642-15277-1_20openalex-snapshot
Code Scheduling for Optimizing Parallelism and Data Locality
inferred← citeshttps://doi.org/10.1007/978-3-642-15291-7_29openalex-snapshot
Optimized Dense Matrix Multiplication on a Many-Core Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-16327-2_27openalex-snapshot
An Efficient Data Indexing Approach on Hadoop Using Java Persistence API
inferred← citeshttps://doi.org/10.1007/978-3-642-28652-0_6openalex-snapshot
Analytical Bounds for Optimal Tile Size Selection
inferred← citeshttps://doi.org/10.1007/978-3-642-57172-5_1openalex-snapshot
A Modern Framework for Portable High-Performance Numerical Linear Algebra
inferred← citeshttps://doi.org/10.1007/978-981-10-8527-7_34openalex-snapshot
Simulation and Application Performance Evaluation Using GPU Through CUDA C & Deep Learning in TensorFlow
inferred← citeshttps://doi.org/10.1007/978-981-13-2721-6_7openalex-snapshot
Data Similarity-Aware Computation Infrastructure for the Cloud
inferred← citeshttps://doi.org/10.1007/b117171openalex-snapshot
Ultra Low-Power Electronics and Design
inferred← citeshttps://doi.org/10.1007/bf01212412openalex-snapshot
Cache tiling for high performance morphological image processing
inferred← citeshttps://doi.org/10.1007/bfb0002746openalex-snapshot
Handling memory cache policy with integer points countings
inferred← citeshttps://doi.org/10.1007/bfb0017243openalex-snapshot
Locality analysis for distributed shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1007/bfb0017262openalex-snapshot
Communication-minimal tiling of uniform dependence loops
inferred← citeshttps://doi.org/10.1007/bfb0032680openalex-snapshot
Quantifying the multi-level nature of tiling interactions
inferred← citeshttps://doi.org/10.1007/bfb0032681openalex-snapshot
Reuse-driven tiling for data locality
inferred← citeshttps://doi.org/10.1007/bfb0038674openalex-snapshot
On estimating and enhancing cache effectiveness
inferred← citeshttps://doi.org/10.1007/bfb0057777openalex-snapshot
On predicting data cache behavior for real-time systems
inferred← citeshttps://doi.org/10.1007/bfb0057949openalex-snapshot
Hardware cache optimization for parallel multimedia applications
inferred← citeshttps://doi.org/10.1007/bfb0100608openalex-snapshot
Efficient analytical modelling of multi-level set-associative caches
inferred← citeshttps://doi.org/10.1007/s00453-006-1224-zopenalex-snapshot
R-Kleene: A High-Performance Divide-and-Conquer Algorithm for the All-Pair Shortest Path for Densely Connected Networks
inferred← citeshttps://doi.org/10.1007/s00500-012-0862-0openalex-snapshot
Fast parallel genetic programming: multi-core CPU versus many-core GPU
inferred← citeshttps://doi.org/10.1007/s00778-018-0533-6openalex-snapshot
Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins
inferred← citeshttps://doi.org/10.1007/s10044-007-0065-yopenalex-snapshot
Exploiting computer resources for fast nearest neighbor classification
inferred← citeshttps://doi.org/10.1007/s10766-005-3581-7openalex-snapshot
Empirical Optimization for a Sparse Linear Solver: A Case Study
inferred← citeshttps://doi.org/10.1007/s10766-009-0113-xopenalex-snapshot
Parallel Lattice Boltzmann Method with Blocked Partitioning
inferred← citeshttps://doi.org/10.1007/s10766-021-00694-2openalex-snapshot
Monoparametric Tiling of Polyhedral Programs
inferred← citeshttps://doi.org/10.1007/s11042-014-1962-xopenalex-snapshot
Joint-Rerank: a novel method for image search reranking
inferred← citeshttps://doi.org/10.1007/s11227-005-0298-8openalex-snapshot
Hyperplane Grouping and Pipelined Schedules: How to Execute Tiled Loops Fast on Clusters of SMPs
inferred← citeshttps://doi.org/10.1007/s11227-007-0106-8openalex-snapshot
Cache oblivious algorithms for nonserial polyadic programming
inferred← citeshttps://doi.org/10.1007/s11227-012-0770-1openalex-snapshot
Enhancing GPU parallelism in nature-inspired algorithms
inferred← citeshttps://doi.org/10.1007/s11227-013-0916-9openalex-snapshot
High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study
inferred← citeshttps://doi.org/10.1007/s11227-021-03642-6openalex-snapshot
High-performance simulations of turbulent boundary layer flow using Intel Xeon Phi many-core processors
inferred← citeshttps://doi.org/10.1007/s11265-005-6650-7openalex-snapshot
Memory Performance Optimizations For Real-Time Software HDTV Decoding
inferred← citeshttps://doi.org/10.1007/s11265-005-6651-6openalex-snapshot
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions
inferred← citeshttps://doi.org/10.1007/s11390-007-9069-8openalex-snapshot
Simultaneous Minimization of Capacity and Conflict Misses
inferred← citeshttps://doi.org/10.1007/s12182-014-0370-1openalex-snapshot
A multilevel preconditioner and its shared memory implementation for a new generation reservoir simulator
inferred← citeshttps://doi.org/10.1016/0167-8191(96)00025-7openalex-snapshot
Characterising and modelling shared memory accesses in multiprocessor programs
inferred← citeshttps://doi.org/10.1016/b978-012170960-0/50019-0openalex-snapshot
Custom Memory Organization and Data Transfer: Architectural Issues and Exploration Methods
inferred← citeshttps://doi.org/10.1016/b978-1-55860-315-8.50017-8openalex-snapshot
References
inferred← citeshttps://doi.org/10.1016/j.asej.2020.01.003openalex-snapshot
Optimizing matrix-matrix multiplication on intel’s advanced vector extensions multicore processor
inferred← citeshttps://doi.org/10.1016/j.compstruc.2011.11.004openalex-snapshot
Parallelized sigma-point Kalman filtering for structural dynamics
inferred← citeshttps://doi.org/10.1016/j.future.2013.10.020openalex-snapshot
Architectural investigation of matrix data layout on multicore processors
inferred← citeshttps://doi.org/10.1016/j.jpdc.2003.09.005openalex-snapshot
Improving effective bandwidth through compiler enhancement of global cache reuse
inferred← citeshttps://doi.org/10.1016/j.jpdc.2004.12.004openalex-snapshot
Improving whole-program locality using intra-procedural and inter-procedural transformations
inferred← citeshttps://doi.org/10.1016/j.jpdc.2005.06.017openalex-snapshot
Efficient synthesis of out-of-core algorithms using a nonlinear optimization solver
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.08.005openalex-snapshot
Data locality and parallelism optimization using a constraint-based approach
inferred← citeshttps://doi.org/10.1016/j.jpdc.2014.03.006openalex-snapshot
Online auto-tuning for the time-step-based parallel solution of ODEs on shared-memory systems
inferred← citeshttps://doi.org/10.1016/j.mejo.2009.12.007openalex-snapshot
Fast field solver for the simulation of large-area OLEDs
inferred← citeshttps://doi.org/10.1016/j.parco.2003.09.004openalex-snapshot
A compiler tool to predict memory hierarchy performance of scientific codes
inferred← citeshttps://doi.org/10.1016/j.parco.2006.07.003openalex-snapshot
Message-passing code generation for non-rectangular tiling transformations
inferred← citeshttps://doi.org/10.1016/j.parco.2007.09.006openalex-snapshot
Cache-efficient numerical algorithms using graphics hardware
inferred← citeshttps://doi.org/10.1016/j.parco.2011.05.002openalex-snapshot
Parallel solution of partial symmetric eigenvalue problems from electronic structure calculations
inferred← citeshttps://doi.org/10.1016/j.parco.2018.11.002openalex-snapshot
Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution
inferred← citeshttps://doi.org/10.1016/j.procs.2015.05.315openalex-snapshot
Optimal Temporal Blocking for Stencil Computation
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.05.001openalex-snapshot
A predictable hardware to exploit temporal reuse in real-time and embedded systems
inferred← citeshttps://doi.org/10.1016/s0024-3795(97)10035-0openalex-snapshot
Practical task-oriented parallelism for Gaussian elimination in distributed memory
inferred← citeshttps://doi.org/10.1016/s0165-1684(97)00041-8openalex-snapshot
Optimal cache usage for separable image processing algorithms on general purpose workstations
inferred← citeshttps://doi.org/10.1016/s0167-8191(00)00040-5openalex-snapshot
Generating efficient tiled code for distributed memory machines
inferred← citeshttps://doi.org/10.1016/s1383-7621(00)00020-5openalex-snapshot
A scheduling policy for preserving cache locality in a multiprogrammed system
inferred← citeshttps://doi.org/10.1016/s1383-7621(03)00040-7openalex-snapshot
Highly accurate and efficient evaluation of randomising set index functions
inferred← citeshttps://doi.org/10.1016/s1383-7621(98)00071-xopenalex-snapshot
SUPPLE: An efficient run-time support for non-uniform parallel loops
inferred← citeshttps://doi.org/10.1016/s1474-6670(17)41383-8openalex-snapshot
Cache-Based Checkpointing for Preemptive Real-Time Systems *
inferred← citeshttps://doi.org/10.1017/s0956796802004458openalex-snapshot
Single Assignment C: efficient support for high-level array operations in a functional setting
inferred← citeshttps://doi.org/10.1023/a:1008193114940openalex-snapshot
Symbolic Cache Analysis for Real-Time Systems
inferred← citeshttps://doi.org/10.1023/a:1010957814813openalex-snapshot
Compilation of Vector Statements of C[] Language for Architectures with Multilevel Memory Hierarchy
inferred← citeshttps://doi.org/10.1023/a:1011119519789openalex-snapshot
Improving Memory Hierarchy Performance for Irregular Applications Using Data and Computation Reorderings
inferred← citeshttps://doi.org/10.1023/a:1011172104768openalex-snapshot
Data-Centric Transformations for Locality Enhancement
inferred← citeshttps://doi.org/10.1023/a:1012293814832openalex-snapshot
Synthesizing Transformations for Locality Enhancement of Imperfectly-Nested Loop Nests
inferred← citeshttps://doi.org/10.1023/a:1013535431127openalex-snapshot
Precise Data Locality Optimization of Nested Loops
inferred← citeshttps://doi.org/10.1023/a:1014156327748openalex-snapshot
An I/O-Conscious Tiling Strategy for Disk-Resident Data Sets
inferred← citeshttps://doi.org/10.1023/a:1014982819342openalex-snapshot
Reducing Cache Conflicts by Multi-Level Cache Partitioning and Array Elements Mapping
inferred← citeshttps://doi.org/10.1023/a:1015460304860openalex-snapshot
Achieving Scalable Locality with Time Skewing
inferred← citeshttps://doi.org/10.1023/a:1018754616274openalex-snapshot
Combining Loop Transformations Considering Caches and Scheduling
inferred← citeshttps://doi.org/10.1023/a:1018780200739openalex-snapshot
Tuning Compiler Optimizations for Simultaneous Multithreading
inferred← citeshttps://doi.org/10.1023/a:1018782528453openalex-snapshot
Quantifying the Multi-Level Nature of Tiling Interactions
inferred← citeshttps://doi.org/10.1023/a:1020989410030openalex-snapshot
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation
inferred← citeshttps://doi.org/10.1023/a:1022340119745openalex-snapshot
Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications
inferred← citeshttps://doi.org/10.1023/a:1024556711058openalex-snapshot
Restructuring Computations for Temporal Data Cache Locality
inferred← citeshttps://doi.org/10.1023/b:supe.0000011386.69245.f5openalex-snapshot
Transforming Complex Loop Nests for Locality
inferred← citeshttps://doi.org/10.1023/b:supe.0000011388.54204.8eopenalex-snapshot
A Quantitative Analysis of Tile Size Selection Algorithms
inferred← citeshttps://doi.org/10.1049/iet-cdt.2009.0066openalex-snapshot
Instruction cache tuning for embedded multitasking applications
inferred← citeshttps://doi.org/10.1049/iet-cdt:20060181openalex-snapshot
Exploiting parallelism in configurable architectures through custom array mapping
inferred← citeshttps://doi.org/10.1063/1.2159147openalex-snapshot
Chaos in computer performance
inferred← citeshttps://doi.org/10.1080/17445760902758560openalex-snapshot
Generic support of algorithmic and structural recursion for scientific computing1
inferred← citeshttps://doi.org/10.1080/17517575.2012.665483openalex-snapshot
An enhanced dynamic hash TRIE algorithm for lexicon search
inferred← citeshttps://doi.org/10.1088/1742-6596/1260/4/042001openalex-snapshot
Cache-aware algorithm for multidimensional correlations
inferred← citeshttps://doi.org/10.1093/comjnl/40.6.373openalex-snapshot
Linear and Extended Linear Transformations for Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1093/mnras/stz3028openalex-snapshot
Direct wide-field radio imaging in real-time at high time resolution using antenna electric fields
inferred← citeshttps://doi.org/10.1109/12.260632openalex-snapshot
Introducing a new cache design into vector computers
inferred← citeshttps://doi.org/10.1109/12.589219openalex-snapshot
Skewed associativity improves program performance and enhances predictability
inferred← citeshttps://doi.org/10.1109/12.752655openalex-snapshot
Augmenting loop tiling with data alignment for improved cache performance
inferred← citeshttps://doi.org/10.1109/12.752657openalex-snapshot
Improving cache locality by a combination of loop and data transformations
inferred← citeshttps://doi.org/10.1109/12.752660openalex-snapshot
Randomized cache placement for eliminating conflicts
inferred← citeshttps://doi.org/10.1109/12.754999openalex-snapshot
A comparative analysis of cache designs for vector processing
inferred← citeshttps://doi.org/10.1109/12.805152openalex-snapshot
Analytical modeling of set-associative cache behavior
inferred← citeshttps://doi.org/10.1109/12.947000openalex-snapshot
Data relation vectors: a new abstraction for data optimizations
inferred← citeshttps://doi.org/10.1109/12.966490openalex-snapshot
The Impulse memory controller
inferred← citeshttps://doi.org/10.1109/12.990130openalex-snapshot
Efficient representation scheme for multidimensional array operations
inferred← citeshttps://doi.org/10.1109/2.318580openalex-snapshot
Cache profiling and the SPEC benchmarks: a case study
inferred← citeshttps://doi.org/10.1109/2.375175openalex-snapshot
Tuning memory performance of sequential and parallel programs
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