On the public citation graph
Functional Verification Coverage Measurement and Analysis
0 signed · 156 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11776420_45openalex-snapshot
Active Sampling for Multiple Output Identification
inferred← citeshttps://doi.org/10.1007/978-0-387-09661-2_4openalex-snapshot
Specification-based Verification of Embedded Systems by Automated Test Case Generation
inferred← citeshttps://doi.org/10.1007/978-1-4419-8034-2_2openalex-snapshot
The Verification Universe
inferred← citeshttps://doi.org/10.1007/978-3-030-66494-7_5openalex-snapshot
Gaining Confidence in the Trustworthiness of Robotic and Autonomous Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-05574-4_5openalex-snapshot
AMS Enhanced Functional Coverage Verification Environment
inferred← citeshttps://doi.org/10.1007/978-3-031-13074-8_14openalex-snapshot
Machine Learning in the Service of Hardware Functional Verification
inferred← citeshttps://doi.org/10.1007/978-3-319-26287-1_5openalex-snapshot
Coverage-Driven Verification —
inferred← citeshttps://doi.org/10.1007/978-3-319-66284-8_1openalex-snapshot
Making the Case for Safety of Machine Learning in Highly Automated Driving
inferred← citeshttps://doi.org/10.1007/978-3-319-77935-5_7openalex-snapshot
An Efficient Rewriting Framework for Trace Coverage of Symmetric Systems
inferred← citeshttps://doi.org/10.1007/978-3-540-72377-6_13openalex-snapshot
Evolutionary Techniques Applied to Hardware Optimization Problems: Test and Verification of Advanced Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-77966-7_11openalex-snapshot
Using Virtual Coverage to Hit Hard-To-Reach Events
inferred← citeshttps://doi.org/10.1007/978-3-540-77966-7_18openalex-snapshot
Locating Regression Bugs
inferred← citeshttps://doi.org/10.1007/978-3-642-01702-5_10openalex-snapshot
Automatic Boosting of Cross-Product Coverage Using Bayesian Networks
inferred← citeshttps://doi.org/10.1007/978-3-642-01702-5_12openalex-snapshot
Evaluating Workloads Using Comparative Functional Coverage
inferred← citeshttps://doi.org/10.1007/978-3-642-04284-3_16openalex-snapshot
Systematic Model-in-the-Loop Test of Embedded Control Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-19237-1_9openalex-snapshot
Evaluating Workloads Using Multi-comparative Functional Coverage
inferred← citeshttps://doi.org/10.1007/978-3-642-19583-9openalex-snapshot
Hardware and Software: Verification and Testing
inferred← citeshttps://doi.org/10.1007/978-3-642-19583-9_10openalex-snapshot
Reaching Coverage Closure in Post-silicon Validation
inferred← citeshttps://doi.org/10.1007/978-3-642-19583-9_13openalex-snapshot
Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-642-30729-4_7openalex-snapshot
Analysing and Closing Simulation Coverage by Automatic Generation and Verification of Formal Properties from Coverage Reports
inferred← citeshttps://doi.org/10.1007/978-3-642-34188-5_17openalex-snapshot
Reverse Coverage Analysis
inferred← citeshttps://doi.org/10.1007/978-3-642-40627-0_60openalex-snapshot
Beyond Feasibility: CP Usage in Constrained-Random Functional Hardware Verification
inferred← citeshttps://doi.org/10.1007/978-94-007-7194-9_131-1openalex-snapshot
Safe and Trustworthy Human Robot Interaction
inferred← citeshttps://doi.org/10.1007/s10009-009-0119-0openalex-snapshot
Using Bayesian networks and virtual coverage to hit hard-to-reach events
inferred← citeshttps://doi.org/10.1007/s10009-010-0160-zopenalex-snapshot
Automatic boosting of cross-product coverage using Bayesian networks
inferred← citeshttps://doi.org/10.1007/s10009-010-0165-7openalex-snapshot
Evaluating workloads using comparative functional coverage
inferred← citeshttps://doi.org/10.1007/s10617-006-9587-6openalex-snapshot
A methodology aimed at better integration of functional verification and RTL design
inferred← citeshttps://doi.org/10.1007/s10617-011-9076-4openalex-snapshot
Enhancing IP cores specifications using hierarchical composition and set theory
inferred← citeshttps://doi.org/10.1007/s10617-016-9178-0openalex-snapshot
Testing real-time embedded systems using high level architecture
inferred← citeshttps://doi.org/10.1007/s10766-005-0005-7openalex-snapshot
Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
inferred← citeshttps://doi.org/10.1007/s10836-010-5184-5openalex-snapshot
A Framework for Automated Detection of Power-related Software Errors in Industrial Verification Processes
inferred← citeshttps://doi.org/10.1007/s10836-011-5219-6openalex-snapshot
Functional Verification of DMA Controllers
inferred← citeshttps://doi.org/10.1007/s10836-011-5225-8openalex-snapshot
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling
inferred← citeshttps://doi.org/10.1007/s10836-012-5308-1openalex-snapshot
Cohesive Coverage Management: Simulation Meets Formal Methods
inferred← citeshttps://doi.org/10.1007/s10836-013-5372-1openalex-snapshot
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
inferred← citeshttps://doi.org/10.1007/s10836-015-5540-6openalex-snapshot
Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm
inferred← citeshttps://doi.org/10.1007/s10994-007-5026-6openalex-snapshot
Active sampling for multiple output identification
inferred← citeshttps://doi.org/10.1007/s11334-019-00348-0openalex-snapshot
Rewriting toward trace coverage analysis of symmetric systems
inferred← citeshttps://doi.org/10.1016/b978-0-12-374364-0.50016-3openalex-snapshot
Functional verification
inferred← citeshttps://doi.org/10.1016/j.asoc.2021.108068openalex-snapshot
Machine learning for hardware security: Classifier-based identification of Trojans in pipelined microprocessors
inferred← citeshttps://doi.org/10.1016/j.ijar.2013.06.004openalex-snapshot
A fuzzy real-time temporal logic
inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102867openalex-snapshot
Understanding multidimensional verification: Where functional meets non-functional
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.02.016openalex-snapshot
There is a limit to everything: Automating AMS operating condition check generation on system-level
inferred← citeshttps://doi.org/10.1049/iet-cdt:20070128openalex-snapshot
Model validation for embedded systems using formal method-aided simulation
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473893openalex-snapshot
Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification
inferred← citeshttps://doi.org/10.1109/cscwd.2017.8066759openalex-snapshot
Extendable generic base verification architecture for flash memory controllers based on UVM
inferred← citeshttps://doi.org/10.1109/csss.2012.48openalex-snapshot
The Research of Parallel CRC Pipeline Algorithm Based on Matrix Transformation
inferred← citeshttps://doi.org/10.1109/csss.2012.522openalex-snapshot
The Design and Implication of Multilevel FPGA Upgrade Online
inferred← citeshttps://doi.org/10.1109/dac.2006.229280openalex-snapshot
Practical methods in coverage-oriented verification of the Merom microprocessor
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218685openalex-snapshot
Late Breaking Results: FRIENDS - Finding Related Interesting Events via Neighbor Detection
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586282openalex-snapshot
Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs
inferred← citeshttps://doi.org/10.1109/dasc.2012.6382383openalex-snapshot
Is the current DO-254 verification process adequate for the future?
inferred← citeshttps://doi.org/10.1109/date.2005.162openalex-snapshot
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
inferred← citeshttps://doi.org/10.1109/date.2007.364491openalex-snapshot
Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design
inferred← citeshttps://doi.org/10.1109/date.2007.364687openalex-snapshot
Design Fault Directed Test Generation for Microprocessor Validation
inferred← citeshttps://doi.org/10.1109/date.2011.5763252openalex-snapshot
A unified methodology for pre-silicon verification and post-silicon validation
inferred← citeshttps://doi.org/10.1109/ddecs.2017.7934589openalex-snapshot
Novel metrics for Analog Mixed-Signal coverage
inferred← citeshttps://doi.org/10.1109/dsd.2005.75openalex-snapshot
Validation of Embedded Systems Using Formal Method Aided Simulation
inferred← citeshttps://doi.org/10.1109/dsd.2013.55openalex-snapshot
Minimal Stimuli Generation in Simulation-Based Verification
inferred← citeshttps://doi.org/10.1109/dsd.2014.100openalex-snapshot
Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation
inferred← citeshttps://doi.org/10.1109/dsd.2015.34openalex-snapshot
Automation and Optimization of Coverage-driven Verification
inferred← citeshttps://doi.org/10.1109/dsd.2016.50openalex-snapshot
Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis
inferred← citeshttps://doi.org/10.1109/eamta.2014.6906085openalex-snapshot
UVM based testbench architecture for unit verification
inferred← citeshttps://doi.org/10.1109/ets61313.2024.10567598openalex-snapshot
Relation Coverage: A New Paradigm for Hardware/Software Testing
inferred← citeshttps://doi.org/10.1109/fdl.2016.7880388openalex-snapshot
Feature based state space coverage of analog circuits
inferred← citeshttps://doi.org/10.1109/fdl.2019.8876957openalex-snapshot
Functional Coverage-Driven Characterization of RF Amplifiers
inferred← citeshttps://doi.org/10.1109/hldvt.2005.1568823openalex-snapshot
Harnessing machine learning to improve the success rate of stimuli generation
inferred← citeshttps://doi.org/10.1109/hldvt.2005.1568842openalex-snapshot
Advanced analysis techniques for cross-product coverage
inferred← citeshttps://doi.org/10.1109/hldvt.2011.6113982openalex-snapshot
Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC
inferred← citeshttps://doi.org/10.1109/hldvt.2011.6114166openalex-snapshot
Introducing XCS to Coverage Directed test Generation
inferred← citeshttps://doi.org/10.1109/hst.2011.5954998openalex-snapshot
Case study: Detecting hardware Trojans in third-party digital IP cores
inferred← citeshttps://doi.org/10.1109/iavvc61942.2025.11219549openalex-snapshot
What did I Learn? Operational Competence Assessment for AI-Based Trajectory Planners
inferred← citeshttps://doi.org/10.1109/icis.2009.34openalex-snapshot
A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit
inferred← citeshttps://doi.org/10.1109/icse-seip58684.2023.00037openalex-snapshot
Achieving Last-Mile Functional Coverage in Testing Chip Design Software Implementations
inferred← citeshttps://doi.org/10.1109/icsmc.2008.4811600openalex-snapshot
Functional verification methodology using Hierarchical Coloured Petri Nets-based testbenches
inferred← citeshttps://doi.org/10.1109/ieeestd.2006.246244openalex-snapshot
IEEE Standard for the Functional Verification Language 'e'
inferred← citeshttps://doi.org/10.1109/ieeestd.2008.4586409openalex-snapshot
IEEE Standard for the Functional Verification Language e
inferred← citeshttps://doi.org/10.1109/isscs52333.2021.9497443openalex-snapshot
Flexible Framework for Stimuli Redundancy Reduction in Functional Verification Using Artificial Neural Networks
inferred← citeshttps://doi.org/10.1109/isvlsi.2007.33openalex-snapshot
Coverage Driven Verification applied to Embedded Software
inferred← citeshttps://doi.org/10.1109/isvlsi.2008.53openalex-snapshot
Cohesive Coverage Management for Simulation and Formal Property Verification
inferred← citeshttps://doi.org/10.1109/itc-asia.2019.00019openalex-snapshot
Did We Test Enough? Functional Coverage for Post-Silicon Validation
inferred← citeshttps://doi.org/10.1109/latw.2009.4813792openalex-snapshot
High-Level Decision Diagrams based coverage metrics for verification and test
inferred← citeshttps://doi.org/10.1109/latw.2009.4813807openalex-snapshot
A method for HW functional verification through HW/SW co-simulation in complex systems: H.264/AVC decoder as case study
inferred← citeshttps://doi.org/10.1109/latw.2011.5985893openalex-snapshot
Evaluating coverage collection using the VEasy functional verification tool suite
inferred← citeshttps://doi.org/10.1109/latw.2018.8349672openalex-snapshot
Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module)
inferred← citeshttps://doi.org/10.1109/mdt.2009.46openalex-snapshot
05 2009 3 3 5167501 10.1109/MDT.2009.45 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5167501 <![CDATA[Are IEEE-1500-Compliant Cores Really Compliant to the Standard?
inferred← citeshttps://doi.org/10.1109/mlcad52597.2021.9531234openalex-snapshot
Using Deep Neural Networks And Derivative Free Optimization To Accelerate Coverage Closure
inferred← citeshttps://doi.org/10.1109/mse.2011.5937102openalex-snapshot
VEasy: A tool suite for teaching VLSI functional verification
inferred← citeshttps://doi.org/10.1109/mtv.2008.20openalex-snapshot
Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution
inferred← citeshttps://doi.org/10.1109/naecon.2010.5712962openalex-snapshot
Formalization of confidence levels in verification efforts
inferred← citeshttps://doi.org/10.1109/ngcas.2018.8572292openalex-snapshot
Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module
inferred← citeshttps://doi.org/10.1109/norchip.2018.8573495openalex-snapshot
Towards Multidimensional Verification: Where Functional Meets Non-Functional
inferred← citeshttps://doi.org/10.1109/norchp.2008.4738278openalex-snapshot
Automatic Verification Plan Generation to Speed up SoC Verification
inferred← citeshttps://doi.org/10.1109/rsp.2008.12openalex-snapshot
A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller
inferred← citeshttps://doi.org/10.1109/sbesc.2015.34openalex-snapshot
Testing Real-Time Embedded Systems with Hardware-in-the-Loop Simulation Using High Level Architecture
inferred← citeshttps://doi.org/10.1109/smacd.2017.7981563openalex-snapshot
Comparing code coverage metrics for analog behavioral models
inferred← citeshttps://doi.org/10.1109/smacd.2017.7981566openalex-snapshot
Comparing apples and oranges: Evaluating model-coverage using acceptance regions
inferred← citeshttps://doi.org/10.1109/systems.2008.4519044openalex-snapshot
Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs
inferred← citeshttps://doi.org/10.1109/tale48869.2020.9368368openalex-snapshot
Selection Criteria of Device under Test and Their Impact on Learning Outcomes of Functional Verification
inferred← citeshttps://doi.org/10.1109/tc.2006.173openalex-snapshot
Advanced Analysis Techniques for Cross-Product Coverage
inferred← citeshttps://doi.org/10.1109/tc.2006.183openalex-snapshot
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
inferred← citeshttps://doi.org/10.1109/tc.2012.163openalex-snapshot
Post-silicon code coverage for multiprocessor system-on-chip designs
inferred← citeshttps://doi.org/10.1109/tcsii.2017.2746744openalex-snapshot
Temporal Coverage Analysis for Dynamic Verification
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2018.8644818openalex-snapshot
An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study
inferred← citeshttps://doi.org/10.1109/vlsi.design.2010.25openalex-snapshot
Coverage Management with Inline Assertions and Formal Test Points
inferred← citeshttps://doi.org/10.1109/wmed71264.2026.11509667openalex-snapshot
Machine Learning-Based Flaky Test Detection and Suppression for UVM Verification Regressions
inferred← citeshttps://doi.org/10.1145/1146909.1146996openalex-snapshot
Practical methods in coverage-oriented verification of the merom microprocessor
inferred← citeshttps://doi.org/10.1145/1218563.1218581openalex-snapshot
Conservative aspect-orientated programming with the e language
inferred← citeshttps://doi.org/10.1145/1278480.1278703openalex-snapshot
Functional verification of sicortex multiprocessor
inferred← citeshttps://doi.org/10.1145/1367045.1367051openalex-snapshot
Specification-driven directed test generation for validation of pipelined processors
inferred← citeshttps://doi.org/10.1145/1529282.1529650openalex-snapshot
Improving functional verification of embedded systems using hierarchical composition and set theory
inferred← citeshttps://doi.org/10.1145/1569901.1570238openalex-snapshot
Automatic detection of software defects
inferred← citeshttps://doi.org/10.1145/2001576.2001749openalex-snapshot
XCS cannot learn all boolean functions
inferred← citeshttps://doi.org/10.1145/2003695.2003698openalex-snapshot
A probabilistic analysis of coverage methods
inferred← citeshttps://doi.org/10.1145/2024724.2024856openalex-snapshot
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
inferred← citeshttps://doi.org/10.1145/2071356.2071363openalex-snapshot
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
inferred← citeshttps://doi.org/10.1145/2380445.2380499openalex-snapshot
A testbench specification language for SystemC verification
inferred← citeshttps://doi.org/10.1145/2593069.2593114openalex-snapshot
Coverage Learned Targeted Validation for Incremental HW Changes
inferred← citeshttps://doi.org/10.1145/2593069.2593183openalex-snapshot
Post-Silicon Validation of the IBM POWER8 Processor
inferred← citeshttps://doi.org/10.1145/2656106.2656113openalex-snapshot
Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators
inferred← citeshttps://doi.org/10.1145/2660540.2660979openalex-snapshot
Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification
inferred← citeshttps://doi.org/10.1145/3107615openalex-snapshot
A Survey on Post-Silicon Functional Validation for Multicore Architectures
inferred← citeshttps://doi.org/10.1145/3380446.3430621openalex-snapshot
Using Machine Learning Clustering To Find Large Coverage Holes
inferred← citeshttps://doi.org/10.1145/3380446.3430627openalex-snapshot
Using DNNs and Smart Sampling for Coverage Closure Acceleration
inferred← citeshttps://doi.org/10.1145/3582016.3582019openalex-snapshot
Simulator Independent Coverage for RTL Hardware Languages
inferred← citeshttps://doi.org/10.1145/3661308openalex-snapshot
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect
inferred← citeshttps://doi.org/10.11606/t.3.2010.tde-20082010-160736openalex-snapshot
Contribuições à verificação funcional ajustada por cobertura para núcleos de hardware de comunicação e multimídia.
inferred← citeshttps://doi.org/10.11606/t.3.2014.tde-23122014-155143openalex-snapshot
Checagem de equivalência de sequências de estados de projetos digitais em RTL com modelos de referência em alto nível e de protocolo de comunicação.
inferred← citeshttps://doi.org/10.12785/ijcds/050207openalex-snapshot
Embedded Systems Design Using Event-B Theories
inferred← citeshttps://doi.org/10.14257/ijca.2014.7.2.20openalex-snapshot
A Specified Coverage Analysis Method Used For Comparison Logic
inferred← citeshttps://doi.org/10.1504/ijcaet.2012.046635openalex-snapshot
Monitoring transaction level SystemC models using a generic and aspect-oriented framework
inferred← citeshttps://doi.org/10.15514/ispras-2014-26(1)-5openalex-snapshot
Tools for Functional Verification of Microprocessors
inferred← citeshttps://doi.org/10.15514/ispras-2017-29(1)-11openalex-snapshot
A Survey of Methods and Tools for Test Program Generation for Microprocessors
inferred← citeshttps://doi.org/10.1561/9781601982193openalex-snapshot
Applied Assertion-Based Verification: An Industry Perspective
inferred← citeshttps://doi.org/10.17586/2226-1494-2018-18-3-479-486openalex-snapshot
Verification of integrated circuit behavioral models by programmable logic
inferred← citeshttps://doi.org/10.17638/datacat.liverpool.ac.uk/177openalex-snapshot
An Assurance-based Approach to Verification and Validation of Human--Robot Teams
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474160openalex-snapshot
Automatic Scalable System for the Coverage-Directed Generation (CDG) Problem
inferred← citeshttps://doi.org/10.2514/6.2013-4565openalex-snapshot
Advanced Verification Techniques for Airborne Safety Critical Hardware
inferred← citeshttps://doi.org/10.2514/6.2025-2326openalex-snapshot
Scenario Coverage of Operational Design Domain for AI-Based Systems in Aviation
inferred← citeshttps://doi.org/10.31114/2078-7707-2021-3-71-75openalex-snapshot
Functional coverage verification methodology for data flow control verification in systems on a chip using SystemVerilog and examples of the interface with the AXI-Stream protocol
inferred← citeshttps://doi.org/10.3176/eng.2010.1.07openalex-snapshot
Application of high-level decision diagrams for simulation-based verification tasks; pp. 56–77
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amm.44-47.3508openalex-snapshot
Guiding Simulation Model Verification by Model Checking
inferred← citeshttps://doi.org/10.4236/opj.2016.610026openalex-snapshot
Unified Coverage Methodology for SoC Post-Silicon Validation
inferred← citeshttps://doi.org/10.48550/arxiv.1509.04852openalex-snapshot
Coverage-Driven Verification - An approach to verify code for robots that directly interact with humans
inferred← citeshttps://doi.org/10.48550/arxiv.2102.02308openalex-snapshot
Fuzzing Hardware Like Software
inferred← citeshttps://doi.org/10.48550/arxiv.2105.08883openalex-snapshot
Deep Neural Network Accelerated Implicit Filtering
inferred← citeshttps://doi.org/10.5555/1266366.1266529openalex-snapshot
Design fault directed test generation for microprocessor validation
inferred← citeshttps://doi.org/10.5555/1266366.1266668openalex-snapshot
Clock domain crossing fault model and coverage metric for validation of SoC design
inferred← citeshttps://doi.org/10.7567/jjap.56.04cf15openalex-snapshot
Property-driven functional verification technique for high-speed vision system-on-chip processor
inferred← citeshttps://doi.org/10.7763/ijiee.2015.v5.504openalex-snapshot
Verification of Embedded System Designs through Hardware-Software Co-Simulation
inferred← citeshttps://doi.org/10.82308/29621openalex-snapshot
Hardware-based temporal logic checkers for the debugging of digital integrated circuits
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.