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Field Programmable Logic and Application
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/1-4020-3128-9_15openalex-snapshot
IPsec-Protected Transport of HDTV over IP
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_105openalex-snapshot
A Statistical Analysis Tool for FPLD Architectures
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_113openalex-snapshot
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_118openalex-snapshot
FPGA Based High Density Spiking Neural Network Array
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_123openalex-snapshot
Hardware-Software Codesign in Embedded Asymmetric Cryptography Application – A Case Study
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_126openalex-snapshot
Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_129openalex-snapshot
Specifying Control Logic for DSP Applications in FPGAs
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_137openalex-snapshot
A Study on the Design of Floating-Point Functions in FPGAs
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_141openalex-snapshot
Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_142openalex-snapshot
Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_146openalex-snapshot
UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_4openalex-snapshot
Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_90openalex-snapshot
From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_93openalex-snapshot
Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_95openalex-snapshot
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_97openalex-snapshot
A TCP/IP Based Multi-device Programming Circuit
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Blob Detection and Labelling
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Remote Batch Invocation for Compositional Object Services
inferred← citeshttps://doi.org/10.1007/978-3-642-15390-7_38openalex-snapshot
An Overview of a Microcontroller-Based Approach to Intelligent Machine Tool Monitoring
inferred← citeshttps://doi.org/10.1007/978-90-481-3913-2_3openalex-snapshot
Deployment of Reconfigurable Systems
inferred← citeshttps://doi.org/10.1016/j.jpdc.2008.06.014openalex-snapshot
Parallel bioinspired algorithms for NP complete graph problems
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103390openalex-snapshot
WITHDRAWN: Different simplified equations for FPGA-based cloud system development and mathematical models
inferred← citeshttps://doi.org/10.1109/cenics.2009.18openalex-snapshot
QCA Implementation of Serpent Block Cipher
inferred← citeshttps://doi.org/10.1109/cscwd.2012.6221935openalex-snapshot
Cloud computing based logistics resource dynamic integration and collaboration
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Better Side-Channel Attacks Through Measurements
inferred← citeshttps://doi.org/10.1201/b15272-3openalex-snapshot
Role of Computational Intelligence in Nanophotonics Technology
inferred← citeshttps://doi.org/10.20868/upm.thesis.69817openalex-snapshot
Contribuciones metodológicas para el desarrollo de aplicaciones de radio software en arquitecturas multiprocesador heterogéneas
inferred← citeshttps://doi.org/10.3390/electronics10060669openalex-snapshot
Coarse-Grained Reconfigurable Computing with the Versat Architecture
inferred← citeshttps://doi.org/10.3390/electronics12010233openalex-snapshot
A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions
inferred← citeshttps://doi.org/10.3390/electronics9101665openalex-snapshot
10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
inferred← citeshttps://doi.org/10.3745/kipstc.2007.14-c.3.209openalex-snapshot
The Design and Implementation of High Performance Intrusion Prevention Algorithm based on Signature Hashing
inferred← citeshttps://doi.org/10.3745/kipstc.2010.17c.2.145openalex-snapshot
Design of Iterative Divider in GF(2163
inferred← citeshttps://doi.org/10.5281/zenodo.192064openalex-snapshot
FIGURE 68. C in Immature stages of Calycopis bellera (Hewitson) and C. janeirica (Felder) (Lepidoptera, Lycaenidae, Theclinae, Eumaeini): Taxonomic significance and new evidence for detritivory
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