On the public citation graph

10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

https://doi.org/10.3390/electronics9101665

0 signed · 56 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/sec.651openalex-snapshot

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

inferredcites →https://doi.org/10.1007/11545262openalex-snapshot

Cryptographic hardware and embedded systems - CHES 2005 : 7th International Workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings

inferredcites →https://doi.org/10.1007/3-540-45682-1_15openalex-snapshot

A Compact Rijndael Hardware Architecture with S-Box Optimization

inferredcites →https://doi.org/10.1007/978-3-319-72823-0openalex-snapshot

5G for Future Wireless Networks

inferredcites →https://doi.org/10.1007/978-3-540-45238-6openalex-snapshot

Cryptographic Hardware and Embedded Systems - CHES 2003

inferredcites →https://doi.org/10.1007/978-3-540-45238-6_26openalex-snapshot

Very Compact FPGA Implementation of the AES Algorithm

inferredcites →https://doi.org/10.1007/978-3-540-68164-9openalex-snapshot

Progress in cryptology-AFRICACRYPT 2008 : first international conference on cryptology in Africa, Casablanca, Morocco, June 11-14, 2008 : proceedings

inferredcites →https://doi.org/10.1007/978-3-642-04101-3openalex-snapshot

Understanding Cryptography: A Textbook For Students And Practitioners

inferredcites →https://doi.org/10.1007/b12007openalex-snapshot

Field Programmable Logic and Application

inferredcites →https://doi.org/10.1007/b99787openalex-snapshot

Field Programmable Logic and Application

inferredcites →https://doi.org/10.1016/j.jksuci.2016.01.004openalex-snapshot

Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA

inferredcites →https://doi.org/10.1049/iet-smt.2018.5664openalex-snapshot

Innovative complete solution for health safety of children unintentionally forgotten in a car: a smart Arduino‐based system with user app for remote control

inferredcites →https://doi.org/10.1049/ip-cds:20030574openalex-snapshot

High-performance FPGA implementation of DES using a novel method for implementing the key schedule

inferredcites →https://doi.org/10.1109/icict43934.2018.9034365openalex-snapshot

Security Measures in IOT based 5G Networks

inferredcites →https://doi.org/10.1109/iscas.2005.1465666openalex-snapshot

An Efficient Architecture for the AES Mix Columns Operation

inferredcites →https://doi.org/10.1109/iscas.2005.1465670openalex-snapshot

AES Crypto Chip Utilizing High-Speed Parallel Pipelined Architecture

inferredcites →https://doi.org/10.1109/isiea.2010.5679375openalex-snapshot

Design of AES S-box using combinational logic optimization

inferredcites →https://doi.org/10.1109/ispacs.2007.4445896openalex-snapshot

Implementations of high throughput sequential and fully pipelined AES processors on FPGA

inferredcites →https://doi.org/10.1109/tc.2003.1190588openalex-snapshot

Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis

inferredcites →https://doi.org/10.1109/vetecf.2004.1400381openalex-snapshot

An implementation of a gigabit ethernet AES encryption engine for application processing in SDR

inferredcites →https://doi.org/10.21307/ijssis-2018-019openalex-snapshot

A ST X-NUCLEO-BASED TELEMETRY UNIT FOR DETECTION AND WiFi TRANSMISSION OF COMPETITION CAR SENSORS DATA: FIRMWARE DEVELOPMENT, SENSORS TESTING AND REAL-TIME DATA ANALYSIS

inferredcites →https://doi.org/10.23919/fpl.2017.8056803openalex-snapshot

High throughput AES encryption/decryption with efficient reordering and merging techniques

inferredcites →https://doi.org/10.24425/ijet.2019.130248openalex-snapshot

Design and Testing of an Electronic Control System Based on STM X-Nucleo Board for Detection and Wireless Transmission of Sensors Data Applied to a Single-Seat Formula SAE Car

inferredcites →https://doi.org/10.29007/x3txopenalex-snapshot

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

inferredcites →https://doi.org/10.3390/electronics8111238openalex-snapshot

Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators

inferredcites →https://doi.org/10.3390/electronics8111247openalex-snapshot

Satellite IoT Edge Intelligent Computing: A Research on Architecture

inferredcites →https://doi.org/10.3390/electronics9060935openalex-snapshot

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

inferredcites →https://doi.org/10.3390/electronics9060957openalex-snapshot

Symmetric-Key Cryptographic Routine Detection in Anti-Reverse Engineered Binaries Using Hardware Tracing

inferredcites →https://doi.org/10.3390/en13092161openalex-snapshot

A Multi-Source Harvesting System Applied to Sensor-Based Smart Garments for Monitoring Workers’ Bio-Physical Parameters in Harsh Environments

inferredcites →https://doi.org/10.3390/en13113024openalex-snapshot

An Energy Model Using Sleeping Algorithms for Wireless Sensor Networks under Proactive and Reactive Protocols: A Performance Evaluation

inferredcites →https://doi.org/10.4236/cs.2014.53007openalex-snapshot

High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

inferredcites →https://doi.org/10.4236/cs.2016.74032openalex-snapshot

Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9781119865513.ch10openalex-snapshot

Cloud Computing Security, Risk, and Challenges

inferred← citeshttps://doi.org/10.1007/978-981-95-7289-2_3openalex-snapshot

Low Power, Area Efficient Very Large-Scale Integration Design of 128_Bit AES Based Cryptography Scheme: A Systematic Review

inferred← citeshttps://doi.org/10.1007/s10791-026-10032-0openalex-snapshot

Enhanced advanced encryption standard algorithm for secure communication with low latency using verilog hardwaredescription language

inferred← citeshttps://doi.org/10.1007/s42979-026-04759-2openalex-snapshot

Quantum-Enhanced Chaotic Encryption on FPGA: A Path to Physical-Layer Post-Quantum Security

inferred← citeshttps://doi.org/10.1016/j.aeue.2025.156187openalex-snapshot

OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption

inferred← citeshttps://doi.org/10.1016/j.jpdc.2024.104898openalex-snapshot

Efficient and lightweight in-memory computing architecture for hardware security

inferred← citeshttps://doi.org/10.1049/ise2/5710384openalex-snapshot

Enhancing E‐Commerce Security Based on Involution Function Using Twin Key AES Cipher

inferred← citeshttps://doi.org/10.1063/5.0317100openalex-snapshot

Enhancing wireless camera security with VLSI-based AES encryption implementation

inferred← citeshttps://doi.org/10.1109/atsip62566.2024.10638850openalex-snapshot

In-Memory Computing Architecture for Efficient Hardware Security

inferred← citeshttps://doi.org/10.1109/cicn70047.2026.11594326openalex-snapshot

Hardware-Efficient Architecture for Secure Underwater Image Transmission Using CNN-Based AES and DNN Encoders

inferred← citeshttps://doi.org/10.1109/hpec67600.2025.11196518openalex-snapshot

Fast FPGA-Based Implementation of the QP-Dyn Stream Cipher using High-Level Synthesis

inferred← citeshttps://doi.org/10.1109/ic_aset58101.2023.10150938openalex-snapshot

A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

inferred← citeshttps://doi.org/10.1109/icsist70215.2026.11705865openalex-snapshot

Context-Aware Adaptive AES-CTR Hardware Accelerator for IoT and Embedded Systems

inferred← citeshttps://doi.org/10.1109/ipdpsw71298.2026.00049openalex-snapshot

Pipelined FPGA Implementation of the QP-DYN Cipher with Scalable Dynamical System Parallelism

inferred← citeshttps://doi.org/10.1109/itc-egypt61547.2024.10620577openalex-snapshot

Area-Optimized FPGA Accelerator for High Throughput Encryption with AXI Integration

inferred← citeshttps://doi.org/10.1109/telsiks52058.2021.9606292openalex-snapshot

Fuzzy AHP based Ranking of Cryptography Indicators

inferred← citeshttps://doi.org/10.1109/tla.2021.9468436openalex-snapshot

A low-cost and highly compact FPGA-based encryption/decryption architecture for AES algorithm

inferred← citeshttps://doi.org/10.1155/2022/1463724openalex-snapshot

[Retracted] Application Research of Data Encryption Algorithm in Computer Security Management

inferred← citeshttps://doi.org/10.14569/ijacsa.2024.0150172openalex-snapshot

Real Time FPGA Implementation of a High Speed for Video Encryption and Decryption System with High Level Synthesis Tools

inferred← citeshttps://doi.org/10.3390/electronics10162023openalex-snapshot

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

inferred← citeshttps://doi.org/10.3390/s21248347openalex-snapshot

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

inferred← citeshttps://doi.org/10.3390/sym18060897openalex-snapshot

Design and Implementation of an AES Hardware Encryption Core

inferred← citeshttps://doi.org/10.37537/rev.elektron.8.2.201.2024openalex-snapshot

Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA

inferred← citeshttps://doi.org/10.48161/qaj.v1n2a38openalex-snapshot

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.