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Field Programmable Logic and Application
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_1openalex-snapshot
FPGAs and the Era of Field Programmability
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_109openalex-snapshot
A Low Power FPAA for Wide Band Applications
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_112openalex-snapshot
Minimum Sum of Absolute Differences Implementation in a Single FPGA Device
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_119openalex-snapshot
An Environment for Exploring Data-Driven Architectures
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_120openalex-snapshot
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_152openalex-snapshot
Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_154openalex-snapshot
Real-Time Detection of Moving Objects
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_155openalex-snapshot
Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_156openalex-snapshot
Versatile Imaging Architecture Based on a System on Chip
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_157openalex-snapshot
A Hardware Implementation of a Content Based Image Retrieval Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_162openalex-snapshot
TPR: Three-D Place and Route for FPGAs
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_164openalex-snapshot
Preemptive Hardware Task Management
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_165openalex-snapshot
Automated Speculation and Parallelism in High Performance Network Applications
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_166openalex-snapshot
Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_170openalex-snapshot
Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_173openalex-snapshot
A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_174openalex-snapshot
On Computing Maximum Likelihood Phylogeny Using FPGA
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_176openalex-snapshot
Application Specific Small-Scale Reconfigurability
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_177openalex-snapshot
Efficient FPGA-Based Security Kernels
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_2openalex-snapshot
Reconfigurable Systems Emerge
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_21openalex-snapshot
On Optimal Irregular Switch Box Designs
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_24openalex-snapshot
Second Order Function Approximation Using a Single Multiplication on FPGAs
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_29openalex-snapshot
Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_5openalex-snapshot
Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_55openalex-snapshot
Automatic Creation of Reconfigurable PALs/PLAs for SoC
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_57openalex-snapshot
High Performance True Random Number Generator in Altera Stratix FPLDs
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_66openalex-snapshot
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_68openalex-snapshot
An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_70openalex-snapshot
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_72openalex-snapshot
SOC and RTOS: Managing IPs and Tasks Communications
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_74openalex-snapshot
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_78openalex-snapshot
An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_9openalex-snapshot
Deploying Hardware Platforms for SoC Validation: An Industrial Case Study
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Blob Detection and Labelling
inferred← citeshttps://doi.org/10.1002/9781119819820.ch2openalex-snapshot
Field‐programmable Gate Arrays
inferred← citeshttps://doi.org/10.1007/978-1-84996-169-1_25openalex-snapshot
Implementing Machine Vision Systems Using FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-36650-5_2openalex-snapshot
CGRA-Hintergrund und verwandte Arbeiten
inferred← citeshttps://doi.org/10.1007/978-3-031-36650-5_3openalex-snapshot
Konzept der Blocks-Architektur
inferred← citeshttps://doi.org/10.1007/978-3-032-17174-0_16openalex-snapshot
Real-Time Stereo Vision Through Optimized FPGA Disparity Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-540-73817-6_8openalex-snapshot
Extracting Microstructure in Binary Constraint Networks
inferred← citeshttps://doi.org/10.1007/978-3-642-21869-9_39openalex-snapshot
Self-assessment of Motivation: Explicit and Implicit Indicators in L2 Vocabulary Learning
inferred← citeshttps://doi.org/10.1007/s00239-020-09982-wopenalex-snapshot
Felsenstein Phylogenetic Likelihood
inferred← citeshttps://doi.org/10.1007/s12652-019-01331-0openalex-snapshot
A lightweight ANN based robust localization technique for rapid deployment of autonomous systems
inferred← citeshttps://doi.org/10.1016/j.comcom.2011.12.009openalex-snapshot
String alignment pre-detection using unique subsequences for FPGA-based network intrusion detection
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2018.02.001openalex-snapshot
Online placement and scheduling algorithm for reconfigurable cells in self-repairable field-programmable gate array systems
inferred← citeshttps://doi.org/10.1016/j.eswa.2012.02.085openalex-snapshot
Compact yet efficient hardware implementation of artificial neural networks with customized topology
inferred← citeshttps://doi.org/10.1016/j.ijleo.2014.06.144openalex-snapshot
Research on active cancelation stealth technique
inferred← citeshttps://doi.org/10.1016/j.jnca.2014.09.006openalex-snapshot
A comprehensive survey of modern symmetric cryptographic solutions for resource constrained environments
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.09.013openalex-snapshot
Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.08.001openalex-snapshot
Multi-character cost-effective and high throughput architecture for content scanning
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.01.002openalex-snapshot
Power consumption models for the use of dynamic and partial reconfiguration
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.01.003openalex-snapshot
A hybrid multiple-character transition finite-automaton for string matching engine
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.07.005openalex-snapshot
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
inferred← citeshttps://doi.org/10.1016/j.micpro.2023.104844openalex-snapshot
Scalable serial hardware architecture of multilayer perceptron neural network for automatic wheezing detection
inferred← citeshttps://doi.org/10.1016/j.micpro.2024.105021openalex-snapshot
Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital
inferred← citeshttps://doi.org/10.1016/j.microrel.2018.02.005openalex-snapshot
A dynamic partial reconfigurable system with combined task allocation method to improve the reliability of FPGA
inferred← citeshttps://doi.org/10.1016/j.patcog.2017.04.018openalex-snapshot
The connected-component labeling problem: A review of state-of-the-art algorithms
inferred← citeshttps://doi.org/10.1016/j.scico.2014.02.015openalex-snapshot
Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging
inferred← citeshttps://doi.org/10.1016/j.sysarc.2011.06.002openalex-snapshot
Fast and efficient FPGA implementation of connected operators
inferred← citeshttps://doi.org/10.1016/j.sysarc.2014.06.002openalex-snapshot
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.05.007openalex-snapshot
Random test program generation for verification and validation of the Samsung Reconfigurable Processor
inferred← citeshttps://doi.org/10.1109/asew.2008.4686290openalex-snapshot
Self-healing strategies for component integration faults
inferred← citeshttps://doi.org/10.1109/iwqos.2017.7969124openalex-snapshot
Which DRM grade could BYOD users employ? A differentiated DRM service between the cloud and mobile devices
inferred← citeshttps://doi.org/10.1109/mwscas.2012.6292059openalex-snapshot
FPGA implementation of fast QR decomposition based on givens rotation
inferred← citeshttps://doi.org/10.1117/12.2053373openalex-snapshot
Towards leakage resiliency: memristor-based AES design for differential power attack mitigation
inferred← citeshttps://doi.org/10.1145/2620728.2620729openalex-snapshot
Flow-level state transition as a new switch primitive for SDN
inferred← citeshttps://doi.org/10.1145/3211332.3211342openalex-snapshot
Verification of coarse-grained reconfigurable arrays through random test programs
inferred← citeshttps://doi.org/10.1145/3242178openalex-snapshot
A Reconfiguration-Based Fault-Tolerant Anti-Lock Brake-by-Wire System
inferred← citeshttps://doi.org/10.1155/2009/450607openalex-snapshot
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms
inferred← citeshttps://doi.org/10.1155/2010/390545openalex-snapshot
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1371/journal.pone.0126517openalex-snapshot
A Memory-Efficient Deterministic Finite Automaton-Based Bit-Split String Matching Scheme Using Pattern Uniqueness in Deep Packet Inspection
inferred← citeshttps://doi.org/10.1371/journal.pone.0163535openalex-snapshot
A Pipelined Non-Deterministic Finite Automaton-Based String Matching Scheme Using Merged State Transitions in an FPGA
inferred← citeshttps://doi.org/10.32560/rk.2019.2.2openalex-snapshot
Az Airbus H145M helikopter fegyverei I. ‒ Nemiránytható rakéta rendszer
inferred← citeshttps://doi.org/10.3390/app11114988openalex-snapshot
Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division
inferred← citeshttps://doi.org/10.3390/electronics15153306openalex-snapshot
Side-Channel Leakage Assessment of an FPGA-Based AES-256 Implementation Using TVLA
inferred← citeshttps://doi.org/10.3390/electronics9101665openalex-snapshot
10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
inferred← citeshttps://doi.org/10.4018/978-1-7998-4570-6.ch003openalex-snapshot
Technologies for Connected Government Implementation
inferred← citeshttps://doi.org/10.5281/zenodo.192064openalex-snapshot
FIGURE 68. C in Immature stages of Calycopis bellera (Hewitson) and C. janeirica (Felder) (Lepidoptera, Lycaenidae, Theclinae, Eumaeini): Taxonomic significance and new evidence for detritivory
inferred← citeshttps://doi.org/10.5772/30186openalex-snapshot
Reconfigurable Systems for Cryptography and Multimedia Applications
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