On the public citation graph

NuMesh: An architecture optimized for scheduled communication

https://doi.org/10.1007/bf00130111
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/71.219761openalex-snapshot
Deadlock-free adaptive routing in multicomputer networks using virtual channels
inferredcites →https://doi.org/10.1109/71.372779openalex-snapshot
Distributed synchronous clocking
inferredcites →https://doi.org/10.1109/superc.1988.44670openalex-snapshot
iWarp: an integrated solution to high-speed parallel computing
inferredcites →https://doi.org/10.1109/tc.1987.1676922openalex-snapshot
Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/tpds.2004.1264792openalex-snapshot
IEEE Transactions on Parallel and Distributed Systems
inferredcites →https://doi.org/10.1145/115952.115975openalex-snapshot
Scheduling pipelined communication in distributed memory multiprocessors for real-time applications
inferredcites →https://doi.org/10.1145/115953.115975openalex-snapshot
Scheduling pipelined communication in distributed memory multiprocessors for real-time applications
inferredcites →https://doi.org/10.1145/130823.130824openalex-snapshot
SPLASH
inferredcites →https://doi.org/10.1145/165939.165973openalex-snapshot
The NuMesh
inferredcites →https://doi.org/10.5555/62972.63015openalex-snapshot
iWarp: an integrated solution to high-speed parallel computing

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4419-0263-4_1openalex-snapshot
Tiled Multicore Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-28641-7_6openalex-snapshot
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture
inferred← citeshttps://doi.org/10.1007/s11227-006-0016-1openalex-snapshot
Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture
inferred← citeshttps://doi.org/10.1109/2.612254openalex-snapshot
Baring it all to software: Raw machines
inferred← citeshttps://doi.org/10.1109/acssc.2001.987684openalex-snapshot
Adaptive systems on a chip (aSoC) for low-power signal processing
inferred← citeshttps://doi.org/10.1109/fccm.2006.55openalex-snapshot
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
inferred← citeshttps://doi.org/10.1109/isca.2004.1310759openalex-snapshot
Evaluation of the raw microprocessor: an exposed-wire-delay architecture for ILP and streams
inferred← citeshttps://doi.org/10.1109/isca.2004.1310771openalex-snapshot
Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor
inferred← citeshttps://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferred← citeshttps://doi.org/10.1109/pact.2000.888329openalex-snapshot
ASOC: a scalable, single-chip communications architecture
inferred← citeshttps://doi.org/10.1109/tc.2013.174openalex-snapshot
An FPGA-Based Reconfigurable Mesh Many-Core
inferred← citeshttps://doi.org/10.1109/tvlsi.2004.830919openalex-snapshot
An architecture and compiler for scalable on-chip communication
inferred← citeshttps://doi.org/10.1145/1028176.1006714openalex-snapshot
Synchroscalar
inferred← citeshttps://doi.org/10.1145/1028176.1006733openalex-snapshot
Evaluation of the Raw Microprocessor
inferred← citeshttps://doi.org/10.1145/1375657.1375669openalex-snapshot
A domain specific interconnect for reconfigurable computing
inferred← citeshttps://doi.org/10.1145/1379023.1375669openalex-snapshot
A domain specific interconnect for reconfigurable computing
inferred← citeshttps://doi.org/10.1587/transinf.2023edp7204openalex-snapshot
Criticality and Tolerance in Injection Timing in Cup-Stacking Method for Collective Communication
inferred← citeshttps://doi.org/10.7907/wzts-xr26openalex-snapshot
Time-Multiplexed FPGA Overlay Networks on Chip
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