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Packet Switched vs. Time Multiplexed FPGA Overlay Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf00130111openalex-snapshot
NuMesh: An architecture optimized for scheduled communication
inferredcites →https://doi.org/10.1016/j.vlsi.2004.03.002openalex-snapshot
Run-time support for heterogeneous multitasking on reconfigurable SoCs
inferredcites →https://doi.org/10.1016/j.vlsi.2004.03.003openalex-snapshot
HERMES: an infrastructure for low area overhead packet-switching networks on chip
inferredcites →https://doi.org/10.1023/b:bttj.0000047600.45421.6dopenalex-snapshot
ConceptNet — A Practical Commonsense Reasoning Tool-Kit
inferredcites →https://doi.org/10.1109/2.612254openalex-snapshot
Baring it all to software: Raw machines
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/cicc.1995.518231openalex-snapshot
A time-multiplexed FPGA architecture for logic emulation
inferredcites →https://doi.org/10.1109/dac.1982.1585480openalex-snapshot
The Yorktown Simulation Engine
inferredcites →https://doi.org/10.1109/fccm.2006.45openalex-snapshot
GraphStep: A System Architecture for Sparse-Graph Algorithms
inferredcites →https://doi.org/10.1109/fpga.1993.279469openalex-snapshot
Virtual wires: overcoming pin limitations in FPGA-based logic emulators
inferredcites →https://doi.org/10.1109/fpga.1995.241941openalex-snapshot
TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire ™ Compilation
inferredcites →https://doi.org/10.1109/fpga.1995.242049openalex-snapshot
PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs
inferredcites →https://doi.org/10.1109/fpga.2002.1106675openalex-snapshot
Hardware-assisted fast routing
inferredcites →https://doi.org/10.1109/isca.2004.1310771openalex-snapshot
Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor
inferredcites →https://doi.org/10.1109/mdt.2005.108openalex-snapshot
Design, Synthesis, and Test of Networks on Chips
inferredcites →https://doi.org/10.1109/superc.1988.44670openalex-snapshot
iWarp: an integrated solution to high-speed parallel computing
inferredcites →https://doi.org/10.1109/tc.1983.1676169openalex-snapshot
The Performance of Multistage Interconnection Networks for Multiprocessors
inferredcites →https://doi.org/10.1109/tc.1985.6312192openalex-snapshot
Fat-trees: Universal networks for hardware-efficient supercomputing
inferredcites →https://doi.org/10.1109/tvlsi.2004.830919openalex-snapshot
An architecture and compiler for scalable on-chip communication
inferredcites →https://doi.org/10.1145/296399.296431openalex-snapshot
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)
inferredcites →https://doi.org/10.1145/368434.368864openalex-snapshot
Improved algorithms for hypergraph bipartitioning
inferredcites →https://doi.org/10.2307/2003526openalex-snapshot
Mathematical Theory of Connecting Networks and Telephone Traffic
inferredcites →https://doi.org/10.5555/62972.63015openalex-snapshot
iWarp: an integrated solution to high-speed parallel computing
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4614-1225-0_2openalex-snapshot
Intra-FPGA Communication Architectures for Reconfigurable Systems
inferred← citeshttps://doi.org/10.1007/978-1-4614-1225-0_3openalex-snapshot
Building Partially Reconfigurable Systems: Methods and Tools
inferred← citeshttps://doi.org/10.1007/978-1-4614-1225-0_4openalex-snapshot
Self-adaptive Reconfigurable Networks
inferred← citeshttps://doi.org/10.1007/978-1-4614-1225-0_5openalex-snapshot
Reconfigurable CPU Instruction Set Extensions
inferred← citeshttps://doi.org/10.1007/978-1-4614-1362-2_6openalex-snapshot
Switch Design for Soft Interconnection Networks
inferred← citeshttps://doi.org/10.1007/978-1-4614-1791-0_13openalex-snapshot
Accelerating the SPICE Circuit Simulator Using an FPGA: A Case Study
inferred← citeshttps://doi.org/10.1007/978-3-031-80629-2_9openalex-snapshot
Time-Domain-Multiplexed Interconnect
inferred← citeshttps://doi.org/10.1007/978-3-540-71431-6_5openalex-snapshot
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-540-71431-6_6openalex-snapshot
Systematic Customization of On-Chip Crossbar Interconnects
inferred← citeshttps://doi.org/10.1007/s11265-014-0884-1openalex-snapshot
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform
inferred← citeshttps://doi.org/10.1007/s11390-011-1145-4openalex-snapshot
A Resource-Efficient Communication Architecture for Chip Multiprocessors on FPGAs
inferred← citeshttps://doi.org/10.1016/j.mejo.2018.08.013openalex-snapshot
Dual Split-Merge: A high throughput router architecture for FPGAs
inferred← citeshttps://doi.org/10.1016/j.micpro.2006.02.009openalex-snapshot
Stream computations organized for reconfigurable execution
inferred← citeshttps://doi.org/10.1016/j.micpro.2010.09.008openalex-snapshot
A hardwired NoC infrastructure for embedded systems on FPGAs
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.04.011openalex-snapshot
A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip
inferred← citeshttps://doi.org/10.1051/matecconf/202030901014openalex-snapshot
The advancement of cluster based FPGA place & route technic
inferred← citeshttps://doi.org/10.1080/00207210801924586openalex-snapshot
Partially reconfigurable point-to-point FPGA interconnects
inferred← citeshttps://doi.org/10.1109/arith.2007.25openalex-snapshot
Optimistic Parallelization of Floating-Point Accumulation
inferred← citeshttps://doi.org/10.1109/asap.2013.6567557openalex-snapshot
Virtual finite-state-machine architectures for fast compilation and portability
inferred← citeshttps://doi.org/10.1109/asap.2013.6567578openalex-snapshot
Microkernel hypervisor for a hybrid ARM-FPGA platform
inferred← citeshttps://doi.org/10.1109/asap.2015.7245698openalex-snapshot
Custom FPGA-based soft-processors for sparse graph acceleration
inferred← citeshttps://doi.org/10.1109/cit.2010.396openalex-snapshot
Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip
inferred← citeshttps://doi.org/10.1109/coolchips52128.2021.9410322openalex-snapshot
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System
inferred← citeshttps://doi.org/10.1109/csit.2013.6588795openalex-snapshot
Hardware implementation of LU decomposition using dataflow architecture on FPGA
inferred← citeshttps://doi.org/10.1109/dasc-picom-datacom-cyberscitec.2016.110openalex-snapshot
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
inferred← citeshttps://doi.org/10.1109/dasip.2011.6136890openalex-snapshot
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology
inferred← citeshttps://doi.org/10.1109/dfm.2014.21openalex-snapshot
Limits of Statically-Scheduled Token Dataflow Processing
inferred← citeshttps://doi.org/10.1109/fccm.2006.45openalex-snapshot
GraphStep: A System Architecture for Sparse-Graph Algorithms
inferred← citeshttps://doi.org/10.1109/fccm.2009.14openalex-snapshot
Accelerating SPICE Model-Evaluation using FPGAs
inferred← citeshttps://doi.org/10.1109/fccm.2009.41openalex-snapshot
Application Specific Customization and Scalability of Soft Multiprocessors
inferred← citeshttps://doi.org/10.1109/fccm.2011.25openalex-snapshot
Towards Synthesis-Free JIT Compilation to Commodity FPGAs
inferred← citeshttps://doi.org/10.1109/fccm.2015.40openalex-snapshot
Sparse Graph Processing with Soft-Processors
inferred← citeshttps://doi.org/10.1109/fccm.2016.47openalex-snapshot
Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs
inferred← citeshttps://doi.org/10.1109/fccm.2018.00013openalex-snapshot
A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/fccm.2019.00022openalex-snapshot
Impact of FPGA Architecture on Area and Performance of CGRA Overlays
inferred← citeshttps://doi.org/10.1109/fccm.2019.00030openalex-snapshot
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control
inferred← citeshttps://doi.org/10.1109/fpl.2007.4380772openalex-snapshot
An FPGA Based Open Source Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/fpl.2008.4630022openalex-snapshot
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects
inferred← citeshttps://doi.org/10.1109/fpl.2009.5272548openalex-snapshot
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
inferred← citeshttps://doi.org/10.1109/fpl.2011.25openalex-snapshot
Generic Low-Latency NoC Router Architecture for FPGA Computing Systems
inferred← citeshttps://doi.org/10.1109/fpl.2011.26openalex-snapshot
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks
inferred← citeshttps://doi.org/10.1109/fpl.2012.6339135openalex-snapshot
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS
inferred← citeshttps://doi.org/10.1109/fpl.2013.6645515openalex-snapshot
A high-performance overlay architecture for pipelined execution of data flow graphs
inferred← citeshttps://doi.org/10.1109/fpl.2015.7293956openalex-snapshot
Hoplite: Building austere overlay NoCs for FPGAs
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577318openalex-snapshot
LYNX: CAD for FPGA-based networks-on-chip
inferred← citeshttps://doi.org/10.1109/fpl.2018.00013openalex-snapshot
Automatic Topology Optimization for FPGA Interconnect Synthesis
inferred← citeshttps://doi.org/10.1109/fpl.2018.00031openalex-snapshot
A Survey on FPGA Virtualization
inferred← citeshttps://doi.org/10.1109/fpl.2018.00044openalex-snapshot
High Performance Communication on Reconfigurable Clusters
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00048openalex-snapshot
A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2008.4762393openalex-snapshot
Exploring hard and soft networks-on-chip for FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2009.5377665openalex-snapshot
Parallelizing sparse Matrix Solve for SPICE circuit simulation using FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412110openalex-snapshot
FPGA optimized packet-switched NoC using split and merge primitives
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412115openalex-snapshot
Small virtual channel routers on FPGAs through block RAM sharing
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718342openalex-snapshot
System-level FPGA device driver with high-level synthesis support
inferred← citeshttps://doi.org/10.1109/fpt.2015.7393127openalex-snapshot
An adaptive virtual overlay for fast trigger insertion for FPGA debug
inferred← citeshttps://doi.org/10.1109/hpcs.2010.5547065openalex-snapshot
A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00063openalex-snapshot
Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks
inferred← citeshttps://doi.org/10.1109/icesc.2014.17openalex-snapshot
Low-Latency, Low-Area Overhead and High Throughput NoC Architecture for FPGA Based Computing System
inferred← citeshttps://doi.org/10.1109/icfpt51103.2020.00035openalex-snapshot
Fast Linking of Separately-Compiled FPGA Blocks without a NoC
inferred← citeshttps://doi.org/10.1109/icfpt52863.2021.9609867openalex-snapshot
Efficient Queue-Balancing Switch for FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00030openalex-snapshot
Asymmetry in Butterfly Fat Tree FPGA NoC
inferred← citeshttps://doi.org/10.1109/idt.2008.4802459openalex-snapshot
A combined packet and circuit switching routing algorithm for networks-on-chips
inferred← citeshttps://doi.org/10.1109/idt.2009.5404107openalex-snapshot
Exploring multistage interconnection network implementations for FPGA-based MPSOCs
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370271openalex-snapshot
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
inferred← citeshttps://doi.org/10.1109/isca.2016.51openalex-snapshot
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric
inferred← citeshttps://doi.org/10.1109/isca.2018.00067openalex-snapshot
FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs
inferred← citeshttps://doi.org/10.1109/iwsoc.2006.348272openalex-snapshot
A Delay Model for Networks-on-Chip Output-Queuing Router
inferred← citeshttps://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferred← citeshttps://doi.org/10.1109/les.2011.2167713openalex-snapshot
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation
inferred← citeshttps://doi.org/10.1109/mcsoc.2019.00018openalex-snapshot
A Novel SLM-Based Virtual FPGA Overlay Architecture
inferred← citeshttps://doi.org/10.1109/mdt.2011.46openalex-snapshot
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing
inferred← citeshttps://doi.org/10.1109/mssc.2018.2822861openalex-snapshot
Recognized as the Best: The ACM\/SIGDA TCFPGA Hall of Fame for FPGAs and Reconfigurable Computing
inferred← citeshttps://doi.org/10.1109/nocs.2008.4492723openalex-snapshot
A Network of Time-Division Multiplexed Wiring for FPGAs
inferred← citeshttps://doi.org/10.1109/nocs.2008.4492724openalex-snapshot
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
inferred← citeshttps://doi.org/10.1109/reconfig.2008.57openalex-snapshot
Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs
inferred← citeshttps://doi.org/10.1109/reconfig.2011.87openalex-snapshot
The Impact of Global Routing on the Performance of NoCs in FPGAs
inferred← citeshttps://doi.org/10.1109/tc.2024.3365954openalex-snapshot
Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers
inferred← citeshttps://doi.org/10.1109/tcad.2011.2173199openalex-snapshot
${\rm SPICE}^2$ : Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA
inferred← citeshttps://doi.org/10.1109/tcad.2021.3091410openalex-snapshot
Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/tpds.2008.233openalex-snapshot
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
inferred← citeshttps://doi.org/10.1109/tpds.2023.3244589openalex-snapshot
Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer
inferred← citeshttps://doi.org/10.1109/tvlsi.2007.902203openalex-snapshot
Run-Time Integration of Reconfigurable Video Processing Systems
inferred← citeshttps://doi.org/10.1109/vlsi.2008.79openalex-snapshot
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks
inferred← citeshttps://doi.org/10.1145/1353610.1353612openalex-snapshot
Interconnection lengths and delays estimation for communication links in FPGAs
inferred← citeshttps://doi.org/10.1145/1596532.1596539openalex-snapshot
A packet-switched network architecture for reconfigurable computing
inferred← citeshttps://doi.org/10.1145/2019583.2019584openalex-snapshot
Spatial hardware implementation for sparse graph algorithms in GraphStep
inferred← citeshttps://doi.org/10.1145/2380403.2380427openalex-snapshot
A low-overhead interconnect architecture for virtual reconfigurable fabrics
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An analytical model for on-chip interconnects in multimedia embedded systems
inferred← citeshttps://doi.org/10.1145/2700082openalex-snapshot
Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability
inferred← citeshttps://doi.org/10.1145/3020078.3021746openalex-snapshot
Secure Function Evaluation Using an FPGA Overlay Architecture
inferred← citeshttps://doi.org/10.1145/3039902.3039904openalex-snapshot
Collective Communication on FPGA Clusters with Static Scheduling
inferred← citeshttps://doi.org/10.1145/3130218.3130238openalex-snapshot
System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip
inferred← citeshttps://doi.org/10.1145/3241045openalex-snapshot
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug
inferred← citeshttps://doi.org/10.1145/3339861openalex-snapshot
Time-Multiplexed FPGA Overlay Architectures
inferred← citeshttps://doi.org/10.1155/2011/745147openalex-snapshot
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads
inferred← citeshttps://doi.org/10.11606/t.3.2011.tde-22032012-175408openalex-snapshot
Plataforma de co-emulação de falhas em circuitos integrados.
inferred← citeshttps://doi.org/10.14288/1.0073573openalex-snapshot
Coarse and fine grain programmable overlay architectures for FPGAs
inferred← citeshttps://doi.org/10.14288/1.0073805openalex-snapshot
Optimizing network-on-chips for FPGAs
inferred← citeshttps://doi.org/10.14288/1.0167154openalex-snapshot
Broadening the applicability of FPGA-based soft vector processors
inferred← citeshttps://doi.org/10.1504/ijcat.2011.045406openalex-snapshot
A multi-level design methodology of multistage interconnection network for MPSOCs
inferred← citeshttps://doi.org/10.1587/transinf.2022pap0009openalex-snapshot
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System
inferred← citeshttps://doi.org/10.17760/d20253796openalex-snapshot
Privacy preserving computations accelerated using FPGA overlays
inferred← citeshttps://doi.org/10.23919/fpl.2017.8056804openalex-snapshot
Deflection-routed butterfly fat trees on FPGAs
inferred← citeshttps://doi.org/10.32657/10356/69532openalex-snapshot
Architecture centric coarse-grained FPGA overlays
inferred← citeshttps://doi.org/10.3390/fi12040064openalex-snapshot
Revisiting the High-Performance Reconfigurable Computing for Future Datacenters
inferred← citeshttps://doi.org/10.3850/9783981537079_0685openalex-snapshot
Throughput Oriented FPGA Overlays Using DSP Blocks
inferred← citeshttps://doi.org/10.3929/ethz-a-006153077openalex-snapshot
Data Stream Processing on Embedded Devices
inferred← citeshttps://doi.org/10.4018/978-1-60960-086-0.ch009openalex-snapshot
A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture
inferred← citeshttps://doi.org/10.4233/uuid:2e8d335a-4251-41d9-b1fd-1697be9fbf2eopenalex-snapshot
Field Programmable Gate Arrays with Hardwired Networks on Chip
inferred← citeshttps://doi.org/10.48550/arxiv.1606.06460openalex-snapshot
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units
inferred← citeshttps://doi.org/10.5555/1509456.1509561openalex-snapshot
Diastolic arrays: throughput-driven reconfigurable computing
inferred← citeshttps://doi.org/10.5772/67257openalex-snapshot
Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture
inferred← citeshttps://doi.org/10.70675/244664a3z92e0z4f77z970dzf1ee4f55b83bopenalex-snapshot
Co-Design de l’application H264 et implantation sur un NoC-GALS
inferred← citeshttps://doi.org/10.7275/12356707openalex-snapshot
On-Chip Communication and Security in FPGAs
inferred← citeshttps://doi.org/10.7907/8nfz-4y29openalex-snapshot
Packet-Switched On-Chip FPGA Overlay Networks
inferred← citeshttps://doi.org/10.7907/m3tw-7y53.openalex-snapshot
Graph parallel actor language --- a programming language for parallel graph algorithms
inferred← citeshttps://doi.org/10.7907/qvzr-vb52.openalex-snapshot
SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator
inferred← citeshttps://doi.org/10.7907/wzts-xr26openalex-snapshot
Time-Multiplexed FPGA Overlay Networks on Chip
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