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Verification of a multiprocessor cache protocol using simulation relations and higher-order logic

https://doi.org/10.1007/bf00709156
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-52559-9_74openalex-snapshot
Analysis of discrete event coordination
inferredcites →https://doi.org/10.1007/3-540-52559-9_79openalex-snapshot
Formal verification of data type refinement — Theory and practice
inferredcites →https://doi.org/10.1007/978-1-4612-3658-0openalex-snapshot
Current Trends in Hardware Verification and Automated Theorem Proving
inferredcites →https://doi.org/10.1007/978-1-4612-3658-0_1openalex-snapshot
Correctness Properties of the Viper Block Model: The Second Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4openalex-snapshot
VLSI Specification, Verification and Synthesis
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot
HOL: A Proof Generating System for Higher-Order Logic
inferredcites →https://doi.org/10.1016/0304-3975(91)90224-popenalex-snapshot
The existence of refinement mappings
inferredcites →https://doi.org/10.1109/43.3210openalex-snapshot
On the verification of sequential machines at differing levels of abstraction
inferredcites →https://doi.org/10.1109/dac.1988.14760openalex-snapshot
Formal verification of the Sobel image processing chip
inferredcites →https://doi.org/10.1109/tc.1986.1676711openalex-snapshot
Automatic Verification of Sequential Circuits Using Temporal Logic
inferredcites →https://doi.org/10.1109/tse.1984.5010246openalex-snapshot
Protocol Verification via Projections
inferredcites →https://doi.org/10.1109/tse.2004.1274039openalex-snapshot
IEEE Transactions on Software Engineering
inferredcites →https://doi.org/10.1145/41840.41852openalex-snapshot
Hierarchical correctness proofs for distributed algorithms
inferredcites →https://doi.org/10.11575/prism/20004openalex-snapshot
An Implementation of higher order logic
inferredcites →https://doi.org/10.48456/tr-68openalex-snapshot
HOL A machine oriented formulation of higher order logic
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-48683-6_27openalex-snapshot
Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems
inferred← citeshttps://doi.org/10.1007/3-540-56922-7_25openalex-snapshot
Computer-assisted simulation proofs
inferred← citeshttps://doi.org/10.1007/3-540-58179-0_59openalex-snapshot
Ground temporal logic: A logic for hardware verification
inferred← citeshttps://doi.org/10.1007/3-540-60275-5_70openalex-snapshot
Formal verification of counterflow pipeline architecture
inferred← citeshttps://doi.org/10.1007/3-540-60385-9_9openalex-snapshot
State enumeration with abstract descriptions of state machines
inferred← citeshttps://doi.org/10.1007/978-0-387-34878-0_19openalex-snapshot
Verifying Timing Properties of Concurrent Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-540-27813-9_33openalex-snapshot
Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values
inferred← citeshttps://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferred← citeshttps://doi.org/10.1007/bf01383986openalex-snapshot
A formal theory of simulations between infinite automata
inferred← citeshttps://doi.org/10.1007/bfb0031796openalex-snapshot
The need for formal methods for integrated circuit design
inferred← citeshttps://doi.org/10.1007/bfb0055652openalex-snapshot
Checking verifications of protocols and distributed systems by computer
inferred← citeshttps://doi.org/10.1016/0141-9331(94)90109-0openalex-snapshot
A case study in specifying and testing architectural features
inferred← citeshttps://doi.org/10.1016/b978-0-444-89880-7.50021-8openalex-snapshot
A Formal Theory of Simulations Between Infinite Automata
inferred← citeshttps://doi.org/10.1109/71.406955openalex-snapshot
A new approach for the verification of cache coherence protocols
inferred← citeshttps://doi.org/10.1109/hol.1991.596274openalex-snapshot
Learning To Use HOL
inferred← citeshttps://doi.org/10.1109/micro.2010.11openalex-snapshot
Fractal Coherence: Scalably Verifiable Cache Coherence
inferred← citeshttps://doi.org/10.1109/spdp.1993.395553openalex-snapshot
Correctness of a directory-based cache coherence protocol: Early experience
inferred← citeshttps://doi.org/10.1109/tpds.2003.1225053openalex-snapshot
Verifying sequential consistency on shared-memory multiprocessors by model checking
inferred← citeshttps://doi.org/10.1145/196244.196392openalex-snapshot
Fitting formal methods into the design cycle
inferred← citeshttps://doi.org/10.1145/248621.248624openalex-snapshot
Verification techniques for cache coherence protocols
inferred← citeshttps://doi.org/10.1145/285055.285057openalex-snapshot
Formal verification of complex coherence protocols using symbolic state models
inferred← citeshttps://doi.org/10.22028/d291-25889openalex-snapshot
Address spaces and virtual memory : specification, implementation, and correctness
inferred← citeshttps://doi.org/10.2316/journal.202.2004.1.202-1270openalex-snapshot
A Case Study on the Verification of Cache Coherence Protocols
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