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Formal hardware verification methods: A survey

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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-97226-9_24openalex-snapshot

Reasoning about state machines in higher-order logic

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Journal of Automated Reasoning

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Edinburgh LCF

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A Calculus of Communicating Systems

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Impartiality, justice and fairness: The ethics of concurrent termination

inferredcites →https://doi.org/10.1007/3-540-11494-7_22openalex-snapshot

Specification and verification of concurrent systems in CESAR

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The glory of the past

inferredcites →https://doi.org/10.1007/3-540-15670-4_6openalex-snapshot

Executing temporal logic programs

inferredcites →https://doi.org/10.1007/3-540-50302-1_2openalex-snapshot

Using higher-order logic for modular specification of real-time distributed systems

inferredcites →https://doi.org/10.1007/3-540-50302-1_4openalex-snapshot

Applications of temporal logic to the specification of real time systems

inferredcites →https://doi.org/10.1007/3-540-51237-3_7openalex-snapshot

A synthesis of two approaches for verifying finite state concurrent systems

inferredcites →https://doi.org/10.1007/3-540-52148-8_17openalex-snapshot

Timing assumptions and verification of finite-state concurrent systems

inferredcites →https://doi.org/10.1007/3-540-52148-8_20openalex-snapshot

Automated verification of timed transition models

inferredcites →https://doi.org/10.1007/3-540-52148-8_27openalex-snapshot

Formal verification of synchronous circuits based on string-functional semantics: The 7 paillet circuits in boyer-moore

inferredcites →https://doi.org/10.1007/3-540-52148-8_28openalex-snapshot

Combining CTL, trace theory and timing models

inferredcites →https://doi.org/10.1007/3-540-52148-8_6openalex-snapshot

Verifying properties of large sets of processes with network invariants

inferredcites →https://doi.org/10.1007/3-540-52559-9_74openalex-snapshot

Analysis of discrete event coordination

inferredcites →https://doi.org/10.1007/3-540-52590-4_43openalex-snapshot

A unified approach for showing language containment and equivalence between various types of ω-automata

inferredcites →https://doi.org/10.1007/3-540-54430-5_93openalex-snapshot

Model checking and modular verification

inferredcites →https://doi.org/10.1007/3-540-56283-4openalex-snapshot

Specifying Message Passing and Time-Critical Systems with Temporal Logic

inferredcites →https://doi.org/10.1007/978-1-349-15428-9openalex-snapshot

Metalogic

inferredcites →https://doi.org/10.1007/978-1-4471-3544-9_11openalex-snapshot

A Model for Synchronous Switching Circuits and its Theory of Correctness

inferredcites →https://doi.org/10.1007/978-1-4612-3658-0_10openalex-snapshot

Mechanizing Programming Logics in Higher Order Logic

inferredcites →https://doi.org/10.1007/978-1-4612-4886-6openalex-snapshot

Fairness

inferredcites →https://doi.org/10.1007/978-1-4612-9855-7openalex-snapshot

Lectures on Boolean Algebras

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4openalex-snapshot

VLSI Specification, Verification and Synthesis

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_1openalex-snapshot

Implementing Safety-Critical Systems: The VIPER Microprocessor

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_11openalex-snapshot

A Compositional Model of MOS Circuits

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot

A Proof of Correctness of the Viper Microprocessor: The First Level

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot

HOL: A Proof Generating System for Higher-Order Logic

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_4openalex-snapshot

Formal Verification and Implementation of a Microprocessor

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_9openalex-snapshot

Abstraction Mechanisms for Hardware Verification

inferredcites →https://doi.org/10.1007/978-1-4613-8928-6_23openalex-snapshot

On a Decision Method in Restricted Second Order Arithmetic

inferredcites →https://doi.org/10.1007/978-1-4615-1471-8_4openalex-snapshot

Formal Verification of Circuit Designs

inferredcites →https://doi.org/10.1007/978-1-4615-7288-6openalex-snapshot

Introduction to Mathematical Logic

inferredcites →https://doi.org/10.1007/978-3-540-69850-0_12openalex-snapshot

DESIGN AND SYNTHESIS OF SYNCHRONIZATION SKELETONS USING BRANCHING TIME TEMPORAL LOGIC

inferredcites →https://doi.org/10.1007/978-3-642-55481-0openalex-snapshot

Programming in Prolog

inferredcites →https://doi.org/10.1007/978-3-642-59412-0_24openalex-snapshot

Proof of Correctness of Data Representations

inferredcites →https://doi.org/10.1007/978-3-642-68402-9_23openalex-snapshot

Temporal Specifications of Self-Timed Systems

inferredcites →https://doi.org/10.1007/978-3-642-82453-1openalex-snapshot

Logics and Models of Concurrent Systems

inferredcites →https://doi.org/10.1007/978-3-642-82453-1_5openalex-snapshot

In Transition From Global to Modular Temporal Reasoning about Programs

inferredcites →https://doi.org/10.1007/978-3-642-82921-5openalex-snapshot

Control Flow and Data Flow: Concepts of Distributed Programming

inferredcites →https://doi.org/10.1007/978-3-7091-7664-1openalex-snapshot

Temporal Logic

inferredcites →https://doi.org/10.1007/978-94-011-1793-7_16openalex-snapshot

The Notion of Proof in Hardware Verification

inferredcites →https://doi.org/10.1007/978-94-017-0462-5openalex-snapshot

Handbook of Philosophical Logic

inferredcites →https://doi.org/10.1007/bf00243131openalex-snapshot

An approach to systems verification

inferredcites →https://doi.org/10.1007/bf00243132openalex-snapshot

Microprocessor design verification

inferredcites →https://doi.org/10.1007/bf00243133openalex-snapshot

A mechanically verified language implementation

inferredcites →https://doi.org/10.1007/bf00243134openalex-snapshot

A mechanically verified code generator

inferredcites →https://doi.org/10.1007/bf00243135openalex-snapshot

Kit and the short stack

inferredcites →https://doi.org/10.1007/bf00265555openalex-snapshot

Fairness and related properties in transition systems ? a temporal logic to deal with fairness

inferredcites →https://doi.org/10.1007/bf00289507openalex-snapshot

Proof of correctness of data representations

inferredcites →https://doi.org/10.1007/bf00709156openalex-snapshot

Verification of a multiprocessor cache protocol using simulation relations and higher-order logic

inferredcites →https://doi.org/10.1007/bf01257083openalex-snapshot

The temporal logic of branching time

inferredcites →https://doi.org/10.1007/bfb0015727openalex-snapshot

Linear and branching structures in the semantics and logics of reactive systems

inferredcites →https://doi.org/10.1007/bfb0015772openalex-snapshot

The complementation problem for Büchi automata with applications to temporal logic

inferredcites →https://doi.org/10.1007/bfb0017309openalex-snapshot

Concurrency and automata on infinite sequences

inferredcites →https://doi.org/10.1007/bfb0023716openalex-snapshot

Verifying temporal properties of sequential machines without building their state diagrams

inferredcites →https://doi.org/10.1007/bfb0023717openalex-snapshot

Formal verification of digital circuits using symbolic ternary system models

inferredcites →https://doi.org/10.1007/bfb0023727openalex-snapshot

Quantitative temporal reasoning

inferredcites →https://doi.org/10.1007/bfb0025774openalex-snapshot

Design and synthesis of synchronization skeletons using branching time temporal logic

inferredcites →https://doi.org/10.1007/bfb0025785openalex-snapshot

Verification of concurrent programs: Temporal proof principles

inferredcites →https://doi.org/10.1007/bfb0027037openalex-snapshot

Current Trends in Concurrency

inferredcites →https://doi.org/10.1007/bfb0027047openalex-snapshot

Applications of temporal logic to the specification and verification of reactive systems: A survey of current trends

inferredcites →https://doi.org/10.1007/bfb0032042openalex-snapshot

Automata for modeling real-time systems

inferredcites →https://doi.org/10.1007/bfb0036915openalex-snapshot

A hardware semantics based on temporal intervals

inferredcites →https://doi.org/10.1007/bfb0042302openalex-snapshot

Reducibility in analysis of coordination

inferredcites →https://doi.org/10.1016/0020-0190(86)90071-2openalex-snapshot

Limits for automatic verification of finite-state concurrent systems

inferredcites →https://doi.org/10.1016/0022-0000(82)90003-4openalex-snapshot

Process logic: Expressiveness, decidability, completeness

inferredcites →https://doi.org/10.1016/0022-0000(86)90026-7openalex-snapshot

Automata-theoretic techniques for modal logics of programs

inferredcites →https://doi.org/10.1016/0096-0551(80)90011-9openalex-snapshot

Introduction to automata theory, languages, and computation

inferredcites →https://doi.org/10.1016/0167-6423(84)90003-0openalex-snapshot

Adequate proof principles for invariance and liveness properties of concurrent programs

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Modalities for model checking: branching time logic strikes back

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Finiteness is mu-ineffable

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Results on the propositional μ-calculus

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Hierarchical verification of asynchronous circuits using temporal logic

inferredcites →https://doi.org/10.1016/0304-3975(87)90008-9openalex-snapshot

The complementation problem for Büchi automata with applications to temporal logic

inferredcites →https://doi.org/10.1016/0376-5075(82)90108-8openalex-snapshot

Protocol specification, testing, and verification

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Introduction to automata theory, languages and computation

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The correctness problem in computer science

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A computational logic handbook

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Symbolic model checking: 1020 States and beyond

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Temporal and Modal Logic

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The Logical Foundations of Mathematics

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A Computational Logic Handbook

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Can message buffers be axiomatized in linear temporal logic?

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Circal: A calculus for circuit description

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On the models for designing VLSI asynchronous digital systems

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Hardware Verification using Higher Order Logic

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Specification and verification of digital systems using higher-order predicate logic

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Formal hardware verification methodology and its application to a network interface chip

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Automatic verification of asynchronous circuits using temporal logic

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Design and verification of regular synchronous circuits

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Automatic verification of asynchronous circuits using temporal logic

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Proof-Checking, Theorem-Proving, and Program Verification

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Verification of multiprocessor cache protocol using simulation relations and higher-order logic

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Assigning meanings to programs

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Lecture Notes in Computer Science 1205

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Formal verification of hardware correctness: introduction and survey of current research

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On the verification of sequential machines at differing levels of abstraction

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Multilevel verification of MOS circuits

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Analysis of digital circuits through symbolic reduction

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A language for compositional specification and verification of finite state hardware controllers

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1975 International Symposium on Computer Hardware Description Languages and their Applications

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State machines, temporal logic and control: A framework for discrete event systems

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A Model for Hardware Description and Verification

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Formal specification and verification of hardware: a comparative case study

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Semantics of Modechart in real time logic

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A functional approach to formal hardware verification: the MTI experience

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Modelling timing assumption with trace theory

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Verifying pipelined hardware using symbolic logic simulation

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Fixed points vs. infinite generation

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Compositional model checking

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A logic of concrete time intervals

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Real-time logics: complexity and expressiveness

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Explicit clock temporal logic

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Model-checking for real-time systems

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Symbolic model checking: 10/sup 20/ states and beyond

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A Temporal Logic for Multilevel Reasoning about Hardware

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Hardware Verification

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The temporal logic of programs

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A decidable mu-calculus: Preliminary report

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Temporal logic can be more expressive

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Reasoning about infinite computation paths

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A really temporal logic

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Hardware Specification with Temporal Logic: An Example

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Automatic Verification of Sequential Circuits Using Temporal Logic

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Graph-Based Algorithms for Boolean Function Manipulation

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Algorithmic Aspects of Symbolic Switch Network Analysis

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Boolean Analysis of MOS Circuits

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Safety analysis of timing properties in real-time systems

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A methodology for hardware verification based on logic simulation

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Reasoning about networks with many identical finite-state processes

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Proving real-time properties of programs with temporal logic

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Sequential circuit verification using symbolic model checking

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Proof-aided design of verified hardware

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Representing circuits more efficiently in symbolic model checking

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Using BDDs to verify multipliers

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Breadth-first manipulation of SBDD of Boolean functions for vector processing

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Model checking and abstraction

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Imperative functional programming

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Modalities for model checking (extended abstract)

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Checking that finite state concurrent programs satisfy their linear specification

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Proving Liveness Properties of Concurrent Programs

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Synthesis of Communicating Processes from Temporal Logic Specifications

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An axiomatic basis for computer programming

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Communicating sequential processes

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Communicating sequential processes

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An axiomatic basis for computer programming

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COSMOS: a compiled simulator for MOS circuits

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The complexity of propositional linear temporal logics

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Avoiding the state explosion problem in temporal logic model checking

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“Sometimes” and “not never” revisited

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Expressing interesting properties of programs in propositional temporal logic

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Automatic verification of finite-state concurrent systems using temporal logic specifications

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How to cook a temporal proof system for your pet language

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On the temporal analysis of fairness

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"Sometime" is sometimes "not never"

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Specifying Concurrent Program Modules

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A structural induction theorem for processes

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Now you may compose temporal logic specifications

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Decision procedures and expressiveness in the temporal logic of branching time

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Proving real-time properties of programs with temporal logic

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Real-time programming and asynchronous message passing

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Research on Automatic Verification of Finite-State Concurrent Systems

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Annual Review of Computer Science

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SML-a high level language for the design and verification of finite state machines

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An Introduction to Mathematical Logic

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Gedanken-Experiments on Sequential Machines

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A Methodology for Hardware Verification Based on Logic Simulation.

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A Temporal Logic for Multi-Level Reasoning About Hardware,

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An Introduction to Modal Logic.

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Metalogic: An Introduction to the Metatheory of Standard First Order Logic.

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Proceedings of the 51st Hawaii International Conference on System Sciences

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Software specification languages based on regular expressions

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Formal verification of basic memory devices

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Using recursive types to reason about hardware in higher order logic

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Formalizing abstraction mechanisms for hardware verification in higher order logic

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LCF_LSM, A system for specifying and verifying hardware

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HOL A machine oriented formulation of higher order logic

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Hardware verification using higher-order logic

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Proving circuit correctness using formal comparison between expected and extracted behaviour

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A Model for Hardware Description and Verification

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The application of program verification techniques to hardware verification

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Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment

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Trace theory and VLSI design

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Verifying a Static RAM Design by Logic Simulation

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