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MSSM—A design aid for multi-stage systolic mapping

https://doi.org/10.1007/bf00925118
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1109/12.9735openalex-snapshot
Synthesizing linear array algorithms from nested FOR loop algorithms
inferredcites →https://doi.org/10.1109/icassp.1985.1168513openalex-snapshot
Systematic approaches to the design of algorithmically specified systolic arrays
inferredcites →https://doi.org/10.1109/icassp.1990.116072openalex-snapshot
Parameterized dependence graph and its applications to multi-stage systolic mapping procedure
inferredcites →https://doi.org/10.1109/massp.1985.1163741openalex-snapshot
VLSI Array processors
inferredcites →https://doi.org/10.1109/mc.1985.1662798openalex-snapshot
A Transformational Model of VLSI Systolic Design
inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot
On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/proc.1984.12944openalex-snapshot
On supercomputing with systolic/wavefront array processors
inferredcites →https://doi.org/10.1109/tc.1982.1675929openalex-snapshot
On the Analysis and Synthesis of VLSI Algorithms
inferredcites →https://doi.org/10.1109/tc.1985.1676516openalex-snapshot
The Design of Optimal Systolic Arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676652openalex-snapshot
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
inferredcites →https://doi.org/10.1117/12.960497openalex-snapshot
What is a Systolic Algorithm?
inferredcites →https://doi.org/10.1137/0714012openalex-snapshot
Least Squares Estimation of Discrete Linear Dynamic Systems Using Orthogonal Transformations
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1145/800015.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1184/r1/6603170openalex-snapshot
An algebra for VLSI algorithm design

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/047134608x.w7220openalex-snapshot
Vlsi Signal Processing
inferred← citeshttps://doi.org/10.1007/bf00924523openalex-snapshot
VASS—A VLSI array system synthesizer
inferred← citeshttps://doi.org/10.1007/bf02106827openalex-snapshot
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays
inferred← citeshttps://doi.org/10.1016/b978-012170960-0/50067-0openalex-snapshot
VLSI Signal Processing
inferred← citeshttps://doi.org/10.1016/j.jpdc.2013.03.003openalex-snapshot
Fine-grained multi-phase array designs
inferred← citeshttps://doi.org/10.1109/43.748156openalex-snapshot
Processor array design with FPGA area constraint
inferred← citeshttps://doi.org/10.1109/71.995819openalex-snapshot
Systolic opportunities for multidimensional data streams
inferred← citeshttps://doi.org/10.1109/76.473553openalex-snapshot
A novel modular systolic array architecture for full-search block matching motion estimation
inferred← citeshttps://doi.org/10.1109/asap.1992.218575openalex-snapshot
ARREST: an interactive graphic analysis tool for VLSI arrays
inferred← citeshttps://doi.org/10.1109/asap.1992.218582openalex-snapshot
On systolic mapping of multi-stage algorithms
inferred← citeshttps://doi.org/10.1109/asap.1994.331811openalex-snapshot
Register transfer modeling and simulation for array processors
inferred← citeshttps://doi.org/10.1109/asap.2002.1030700openalex-snapshot
Compositional technique for synthesising multi-phase regular arrays
inferred← citeshttps://doi.org/10.1109/icassp.1995.479439openalex-snapshot
Optimal VLSI architecture for vector quantization
inferred← citeshttps://doi.org/10.1109/icassp.1995.479691openalex-snapshot
A novel modular systolic array architecture for full-search block matching motion estimation
inferred← citeshttps://doi.org/10.1109/iscas.1994.408922openalex-snapshot
Is it possible to achieve a teraflop/s on a chip? From high performance algorithms to architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2358196openalex-snapshot
Systolic Array Architectures for Sunar–Koç Optimal Normal Basis Type II Multiplier
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