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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-68402-9openalex-snapshot

VLSI Systems and Computations

inferredcites →https://doi.org/10.1007/978-3-642-68402-9_25openalex-snapshot

A Wavefront Notation Tool for VLSI Array Design

inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot

Introduction to V.L.S.I. Systems

inferredcites →https://doi.org/10.1109/mc.1982.1653825openalex-snapshot

Why systolic architectures?

inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot

On the design of algorithms for VLSI systolic arrays

inferredcites →https://doi.org/10.1112/blms/2.3.373bopenalex-snapshot

DIOPHANTINE EQUATIONS

inferredcites →https://doi.org/10.1137/1013094openalex-snapshot

A Survey of Parallelism in Numerical Analysis

inferredcites →https://doi.org/10.1145/356683.356686openalex-snapshot

A Survey of Parallel Machine Organization and Programming

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A systematic method of synthesizing systolic arrays using a data dependence graph

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Parallelization of the Gaussian Elimination Algorithm on Systolic Arrays

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Changing Challenges for Collaborative Algorithmics

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Synthesis and equivalence of concurrent systems

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On synthesizing systolic arrays from Recurrence Equations with Linear Dependencies

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An implemented method for incremental systolic design

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Systolic array synthesis by static analysis of program dependencies

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An introduction to systolic architectures

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Systolic architectures, systems and computations

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Efficient Parallelisation of Recursive Problems Using Constructive Recursion

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Porting generalized eigenvalue software on distributed memory machines using systolic model principles

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Parallel Numerical Algorithms for Distributed Memory Machines

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Single-assignment semantics for imperative programs

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Loop parallelization in the polytope model

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Compiler Techniques for Massive Parallel Architectures

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Affine Permutations of Matrices on Mesh-Connected Arrays

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Control Generation in the Design of Processor Arrays

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The SDEF Systolic Programming System

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Ensemble Architectures and their Algorithms: An Overview

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Regularising Transformations for Integral Dependencies

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Relocalization of Data Dependences in Partitioned Affine Indexed Algorithms

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Systolic arrays for multidimensional discrete transforms

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The derivation of systolic implementations of programs

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Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays

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MSSM—A design aid for multi-stage systolic mapping

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Control generation in the design of processor arrays

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Multidimensional fourier transforms by systolic architectures

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Formalized design of systolic processors: The example of processors for triangular decomposition of symmetrical matrices

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Systolic parsing of context-free languages

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Synthesizing systolic arrays with control signals from recurrence equations

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Mapping 3-D IIR digital filter onto systolic arrays

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Converting affine recurrence equations to quasi-uniform recurrence equations

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Design techniques for fault-tolerant systolic arrays

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Area efficient computing structures for concurrent error detection in systolic arrays

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Resource constrained scheduling of uniform algorithms

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The application of a sequence notation to the design of systolic computations

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Systolic computation of interpolating polynomials

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Computing transitive closure on systolic arrays of fixed size

inferred← citeshttps://doi.org/10.1007/bf02477176openalex-snapshot

The mapping of linear recurrence equations on regular arrays

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Scheduling a system of nonsingular affine recurrence equations onto a processor array

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Systolic arrays: Characterizations and complexity

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Converting affine recurrence equations to quasi-uniform recurrence equations

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Synthesis of space optimal systolic arrays for band matrix-vector multiplication

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Dynamic programming on two-dimensional systolic arrays

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Decoupling the dimension of a system of affine recurrence equations

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Systematic design of systolic arrays for computing multiple problem instances

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A VLSI systolic architecture for fuzzy clustering

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A DBT-based VLSI systolic architecture for hard squared error clustering

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Synthesis of systolic algorithm design

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Synthesizing systolic arrays from recurrence equations

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Triangular matrix inversion on systolic arrays

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A VLSI systolic architecture for solving DBT-transformed fuzzy clustering problems of arbitrary size

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A systematic approach for designing concurrent error-detecting systolic arrays using redundancy

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Automating the design of systolic arrays

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On the analysis and optimization of selftimed processor arrays

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Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays

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Synthesis and equivalence of concurrent systems

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Two-dimensional iterative arrays: Characterizations and applications

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Synthesis, structure and power of systolic computations

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A design methodology for synthesizing parallel algorithms and architectures

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Systolic structures: A notion and characterization

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Gaussian elimination on a hypercube automaton

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Designing linear systolic arrays

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SOS: Synthesis of application-specific heterogeneous multiprocessor systems

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Transformation of broadcasts into propagations in systolic algorithms

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Designing of processor-time optimal systolic arrays for band matrix-vector multiplication

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CAUSALITY IN ALGORITHMS AND ARCHITECTURES††Invited talk.

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Mapping Algorithms onto VLSI Architectures

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SOS: Synthesis of Application-Specific Heterogeneous Multiprocessor Systems**This work was supported in part by the Department of the Air Force, the Department of the Army, and the Department of the Navy, Contract N00039-87-C-0194, and in part by the Defense Advanced Research Projects Agency,…

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Dataflow-Based Parallelization of Control-Flow Algorithms

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A domain-specific language for structure manipulation in constraint system-based GUIs

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A Hardware Independent Parallel Programming Model

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Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming

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8 VLSI in signal processing

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The design of optimal planar systolic arrays for matrix multiplication

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Computation Algebras

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A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP

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Finding Space-Time Transformations for Uniform Recurrences via Branching Parametric Linear Programming

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On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming

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A Fast Algorithm for Matrix Multiplication and Its Efficient Realization on Systolic Arrays

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An Integrated Approach to the Design of Processor Arrays with Systolic Organization of Computations

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Systolic arrays: how to choose them

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Forty-three ways of systolic matrix multiplication

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Decomposing polynomial interpolation for systolic arrays

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Advanced Regular Array Design

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FINDING OPTIMUM WAVEFRONT OF PARALLEL COMPUTATION∗

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Restructuring for fault-tolerant systolic arrays

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Your favorite parallel algorithms might not be as fast as you think

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The generation of a class of multipliers: synthesizing highly parallel algorithms in VLSI

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On systolic contractions of program graphs

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Design of space-optimal regular arrays for algorithms with linear schedules

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A note on the linear transformation method for systolic array design

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Synthesizing linear array algorithms from nested FOR loop algorithms

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A processor-time-minimal systolic array for cubical mesh algorithms

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Mapping nested loop algorithms into multidimensional systolic arrays

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Partitioning and mapping nested loops on multiprocessor systems

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Bit-level pipelined 2-D digital filters for real-time image processing

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Systolic implementation of multidimensional nonrecursive digital filters

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Some space considerations of VLSI systolic array mappings

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Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme

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Determining objective functions in systolic array designs

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Systolic arrays for integer Chinese remaindering

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Scheduling a system of affine recurrence equations onto a systolic array

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Systolic array implementation of nested loop programs

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A chain-multiplier for large scale matrix multiplication

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Designing parallel algorithms from forests and multistage graphs

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Synthesis of systolic arrays from single assignment algorithm

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Mapping nested loop algorithms into fault-tolerant systolic array architectures

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Mapping recursive algorithms onto systolic architectures

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Mapping Signal Processing Algorithms Into The Systolic Arrays

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Some space considerations of VLSI systolic array mappings

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Derivation of Systolic Programs

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Variations on the theme for designing fault-tolerant systolic array architectures

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Multidimensional Fourier transforms by systolic architectures

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Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems

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Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays

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Automatic Generation of Spatial Accelerator for Tensor Algebra

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3. A Bibliography on Parallel and Vector Numerical Algorithms

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BOUNDED BROADCAST IN SYSTOLIC ARRAYS

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Programmable data dependencies and placements

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Thoughts on parallelism and concurrency in compiling curricula

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Multiplexed pipelining : a cost effective loop transformation technique

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