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Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.40844openalex-snapshot
The nonuniform distribution of instruction-level and machine parallelism and its effect on performance
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/isscc.1990.110121openalex-snapshot
A 500 MHz microprocessor with a very long instruction word architecture
inferredcites →https://doi.org/10.1109/micro.1988.639264openalex-snapshot
Organization Of Array Data For Concurrent Memory Access
inferredcites →https://doi.org/10.1109/superc.1990.130118openalex-snapshot
Architecture and implementation of a VLIW supercomputer
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/1067651.801649openalex-snapshot
Very Long Instruction Word architectures and the ELI-512
inferredcites →https://doi.org/10.1145/106972.106976openalex-snapshot
A variable instruction stream extension to the VLIW architecture
inferredcites →https://doi.org/10.1145/106972.106991openalex-snapshot
Limits of instruction-level parallelism
inferredcites →https://doi.org/10.1145/115952.115971openalex-snapshot
Instruction level profiling and evaluation of the IBM/6000
inferredcites →https://doi.org/10.1145/285930.285985openalex-snapshot
Very long instruction work architectures and the ELI-512
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.2307/2007938openalex-snapshot
Numerical Recipes--The Art of Scientific Computing.
inferredcites →https://doi.org/10.2307/2008673openalex-snapshot
Numerical Recipes in C-The Art of Scientific Computing.
inferredcites →https://doi.org/10.2307/2153422openalex-snapshot
Numerical Recipes in Fortran: The Art of Scientific Computing.
inferredcites →https://doi.org/10.5555/110382.110622openalex-snapshot
Architecture and implementation of a VLIW supercomputer
inferredcites →https://doi.org/10.5555/62504.62672openalex-snapshot
Organization of array data for concurrent memory access
inferredcites →https://doi.org/10.5860/choice.27-5158openalex-snapshot
Numerical recipes in Pascal: the art of scientific computing
inferredcites →https://doi.org/10.5860/choice.30-5638openalex-snapshot
Numerical recipes in C: the art of scientific computing
inferredcites →https://doi.org/10.5860/choice.30-5638aopenalex-snapshot
Numerical recipes in FORTRAN: the art of scientific computing
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4615-3200-2_3openalex-snapshot
Instruction-Level Parallel Processing: History, Overview, and Perspective
inferred← citeshttps://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferred← citeshttps://doi.org/10.1109/5.476079openalex-snapshot
Compiler technology for future microprocessors
inferred← citeshttps://doi.org/10.1109/hicss.1995.375398openalex-snapshot
An architecture for high instruction level parallelism
inferred← citeshttps://doi.org/10.1109/micro.1995.476840openalex-snapshot
Partitioned register file for TTAs
inferred← citeshttps://doi.org/10.48456/tr-588openalex-snapshot
MulTEP: A MultiThreaded Embedded Processor
inferred← citeshttps://doi.org/10.5555/224659.224682openalex-snapshot
Increasing superscalar performance through multistreaming
inferred← citeshttps://doi.org/10.5555/224659.224696openalex-snapshot
The influence of branch prediction table interference on branch prediction scheme performance
inferred← citeshttps://doi.org/10.5555/225160.225207openalex-snapshot
Partitioned register file for TTAs
inferred← citeshttps://doi.org/10.6100/ir808001openalex-snapshot
Compiler Strategies for Transport Triggered Architectures.
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