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Instruction-level parallel processing: History, overview, and perspective
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.4380220502openalex-snapshot
Profile‐guided automatic inline expansion for C programs
inferredcites →https://doi.org/10.1007/3-540-19027-9_15openalex-snapshot
Perfect pipelining: A new loop parallelization technique
inferredcites →https://doi.org/10.1007/978-1-4471-3501-2_9openalex-snapshot
Phase Ordering of Register Allocation and Instruction Scheduling
inferredcites →https://doi.org/10.1007/978-1-4613-1705-0openalex-snapshot
A Systolic Array Optimizing Compiler
inferredcites →https://doi.org/10.1007/bf00288685openalex-snapshot
Optimal scheduling for two-processor systems
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1007/bf01205183openalex-snapshot
The cydra 5 minisupercomputer: Architecture and implementation
inferredcites →https://doi.org/10.1007/bf01205185openalex-snapshot
The superblock: An effective technique for VLIW and superscalar compilation
inferredcites →https://doi.org/10.1007/bf01205186openalex-snapshot
Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer
inferredcites →https://doi.org/10.1007/bfb0038653openalex-snapshot
Languages and Compilers for Parallel Computing
inferredcites →https://doi.org/10.1007/bfb0038668openalex-snapshot
Data flow and dependence analysis for instruction level parallelism
inferredcites →https://doi.org/10.1017/s0305004100028322openalex-snapshot
Micro-programming and the design of the control circuits in an electronic digital computer
inferredcites →https://doi.org/10.1109/12.2247openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1109/12.372029openalex-snapshot
The importance of prepass code scheduling for superscalar and superpipelined processors
inferredcites →https://doi.org/10.1109/12.40844openalex-snapshot
The nonuniform distribution of instruction-level and machine parallelism and its effect on performance
inferredcites →https://doi.org/10.1109/12.4607openalex-snapshot
Implementing precise interrupts in pipelined processors
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/2.30730openalex-snapshot
Dynamic instruction scheduling and the Astronautics ZS-1
inferredcites →https://doi.org/10.1109/40.127582openalex-snapshot
Organization of the Motorola 88110 superscalar RISC microprocessor
inferredcites →https://doi.org/10.1109/40.31485openalex-snapshot
Introducing the Intel i860 64-bit microprocessor
inferredcites →https://doi.org/10.1109/40.87565openalex-snapshot
IBM RISC System/6000: architecture and performance
inferredcites →https://doi.org/10.1109/40.87567openalex-snapshot
Datawave: a single-chip multiprocessor for video applications
inferredcites →https://doi.org/10.1109/40.87568openalex-snapshot
iWarp: a 100-MOPS, LIW microprocessor for multicomputers
inferredcites →https://doi.org/10.1109/c-m.1981.220595openalex-snapshot
An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family
inferredcites →https://doi.org/10.1109/cmpcon.1988.4840openalex-snapshot
Cydra 5 directed dataflow architecture
inferredcites →https://doi.org/10.1109/cmpcon.1990.63719openalex-snapshot
CREATE-LIFE: a modular design approach for high performance ASICs
inferredcites →https://doi.org/10.1109/cmpcon.1991.128789openalex-snapshot
The DN 10000TX: a new high-performance PRISM processor
inferredcites →https://doi.org/10.1109/cmpcon.1992.186696openalex-snapshot
A high speed superscalar PA-RISC processor
inferredcites →https://doi.org/10.1109/cmpcon.1992.186699openalex-snapshot
The SuperSPARC microprocessor
inferredcites →https://doi.org/10.1109/hicss.1993.270744openalex-snapshot
Software pipelining and superblock scheduling: compilation techniques for VLIW machines
inferredcites →https://doi.org/10.1109/iccd.1988.25722openalex-snapshot
CREATE-LIFE: a design system for high performances VLSI circuits
inferredcites →https://doi.org/10.1109/isca.1988.5209openalex-snapshot
Exploiting parallel microprocessor microarchitectures with a compiler code generator
inferredcites →https://doi.org/10.1109/isca.1990.134511openalex-snapshot
Monsoon: an explicit token-store architecture
inferredcites →https://doi.org/10.1109/isca.1992.753303openalex-snapshot
Limits of Control Flow on Parallelism
inferredcites →https://doi.org/10.1109/isca.1992.753304openalex-snapshot
The Expandable Split Window Paradigm for Exploiting Fine-grain Parallelism
inferredcites →https://doi.org/10.1109/mc.1982.1654020openalex-snapshot
Computer-Aided Specification of Process Control Systems
inferredcites →https://doi.org/10.1109/mc.1984.1658927openalex-snapshot
Branch Prediction Strategies and Branch Target Buffer Design
inferredcites →https://doi.org/10.1109/micro.1990.151422openalex-snapshot
VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors
inferredcites →https://doi.org/10.1109/micro.1990.151427openalex-snapshot
Using a lookahead window in a compaction-based parallelizing compiler
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1992.697031openalex-snapshot
An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts
inferredcites →https://doi.org/10.1109/mm.1984.291304openalex-snapshot
Derek de Solla Price and the Antikythera Mechanism: An Appreciation
inferredcites →https://doi.org/10.1109/proc.1977.10691openalex-snapshot
Introduction to computer architecture
inferredcites →https://doi.org/10.1109/superc.1988.44632openalex-snapshot
A processor architecture for Horizon
inferredcites →https://doi.org/10.1109/superc.1990.130021openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.1109/superc.1990.130118openalex-snapshot
Architecture and implementation of a VLIW supercomputer
inferredcites →https://doi.org/10.1109/t-c.1970.222795openalex-snapshot
Detection and Parallel Execution of Independent Instructions
inferredcites →https://doi.org/10.1109/t-c.1971.223347openalex-snapshot
Optimization Strategies for Microprograms
inferredcites →https://doi.org/10.1109/t-c.1972.223514openalex-snapshot
The Inhibition of Potential Parallelism by Conditional Jumps
inferredcites →https://doi.org/10.1109/t-c.1972.223515openalex-snapshot
Percolation of Code to Enhance Parallel Dispatching and Execution
inferredcites →https://doi.org/10.1109/t-c.1974.224035openalex-snapshot
A High-Level Language for Horizontal Microprogramming
inferredcites →https://doi.org/10.1109/t-c.1975.224171openalex-snapshot
A Preliminary Evaluation of the Critical Path Method for Scheduling Tasks on Multiprocessor Systems
inferredcites →https://doi.org/10.1109/tc.1972.5008918openalex-snapshot
Optimal Scheduling Strategies in a Multiprocessor System
inferredcites →https://doi.org/10.1109/tc.1972.5009044openalex-snapshot
Pipelining of Arithmetic Functions
inferredcites →https://doi.org/10.1109/tc.1973.5009153openalex-snapshot
Bounds on the Number of Processors and Time for Multiprocessor Optimal Schedules
inferredcites →https://doi.org/10.1109/tc.1973.5009154openalex-snapshot
Representation of Concurrency with Ordering Matrices
inferredcites →https://doi.org/10.1109/tc.1973.5009159openalex-snapshot
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
inferredcites →https://doi.org/10.1109/tc.1976.1674537openalex-snapshot
Microprogram Optimization: A Survey
inferredcites →https://doi.org/10.1109/tc.1976.1674539openalex-snapshot
The Identification of Maximal Parallelism in Straight-Line Microprograms
inferredcites →https://doi.org/10.1109/tc.1976.1674540openalex-snapshot
Toward Optimization of Horizontal Microprograms
inferredcites →https://doi.org/10.1109/tc.1981.1675826openalex-snapshot
Some Experiments in Local Microcode Compaction for Horizontal Machines
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1109/tc.1981.1675828openalex-snapshot
Optimization of Microprograms
inferredcites →https://doi.org/10.1109/tc.1983.1676181openalex-snapshot
A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction
inferredcites →https://doi.org/10.1109/tc.1984.1676371openalex-snapshot
Measuring the Parallelism Available for Very Long Instruction Word Architectures
inferredcites →https://doi.org/10.1109/tc.1984.1676376openalex-snapshot
Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
inferredcites →https://doi.org/10.1109/tc.1986.1676841openalex-snapshot
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
inferredcites →https://doi.org/10.1109/tc.1987.5009500openalex-snapshot
Checkpoint Repair for High-Performance Out-of-Order Execution Machines
inferredcites →https://doi.org/10.1137/0204020openalex-snapshot
Complete Register Allocation Problems
inferredcites →https://doi.org/10.1145/1014188.803006openalex-snapshot
Global optimization of microprograms through modular control constructs
inferredcites →https://doi.org/10.1145/1014190.802713openalex-snapshot
2 n -way jump microinstruction hardware and an effective instruction binding method
inferredcites →https://doi.org/10.1145/1014192.802448openalex-snapshot
Using an oracle to measure potential parallelism in single instruction stream programs
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/1014196.803322openalex-snapshot
An approach to microprogram optimization considering resource occupancy and instruction formats
inferredcites →https://doi.org/10.1145/1014198.804306openalex-snapshot
A technique of global optimization of microprograms
inferredcites →https://doi.org/10.1145/1014198.804307openalex-snapshot
On the packing of micro-operations into micro-instruction words
inferredcites →https://doi.org/10.1145/1014198.804314openalex-snapshot
A methodology for programming a pipeline array processor
inferredcites →https://doi.org/10.1145/1067649.801719openalex-snapshot
Decoupled access/execute computer architectures
inferredcites →https://doi.org/10.1145/1067649.801721openalex-snapshot
Efficient code generation for horizontal architectures
inferredcites →https://doi.org/10.1145/1067651.801649openalex-snapshot
Very Long Instruction Word architectures and the ELI-512
inferredcites →https://doi.org/10.1145/106972.106976openalex-snapshot
A variable instruction stream extension to the VLIW architecture
inferredcites →https://doi.org/10.1145/106972.106991openalex-snapshot
Limits of instruction-level parallelism
inferredcites →https://doi.org/10.1145/106973.106991openalex-snapshot
Limits of instruction-level parallelism
inferredcites →https://doi.org/10.1145/1096503.1096504openalex-snapshot
Using a lookahead window in a compaction-based parallelizing compiler
inferredcites →https://doi.org/10.1145/113445.113462openalex-snapshot
Register allocation via hierarchical graph coloring
inferredcites →https://doi.org/10.1145/113445.113466openalex-snapshot
Global instruction scheduling for superscalar machines
inferredcites →https://doi.org/10.1145/115952.115980openalex-snapshot
Single instruction stream parallelism is greater than two
inferredcites →https://doi.org/10.1145/115953.115980openalex-snapshot
Single instruction stream parallelism is greater than two
inferredcites →https://doi.org/10.1145/12276.13312openalex-snapshot
Efficient instruction scheduling for a pipelined architecture
inferredcites →https://doi.org/10.1145/123465.123482openalex-snapshot
Efficient DAG construction and heuristic calculation for instruction scheduling
inferredcites →https://doi.org/10.1145/139669.139709openalex-snapshot
Alternative implementations of two-level adaptive branch prediction
inferredcites →https://doi.org/10.1145/143095.143141openalex-snapshot
Register allocation for software pipelined loops
inferredcites →https://doi.org/10.1145/143365.143529openalex-snapshot
Sentinel scheduling for VLIW and superscalar processors
inferredcites →https://doi.org/10.1145/143365.143534openalex-snapshot
Efficient superscalar performance through boosting
inferredcites →https://doi.org/10.1145/143369.143419openalex-snapshot
Register requirements of pipelined processors
inferredcites →https://doi.org/10.1145/144965.145000openalex-snapshot
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
inferredcites →https://doi.org/10.1145/144965.145796openalex-snapshot
Enhanced modulo scheduling for loops with conditional branches
inferredcites →https://doi.org/10.1145/1460299.1460304openalex-snapshot
The engineering design of the stretch computer
inferredcites →https://doi.org/10.1145/1460299.1460305openalex-snapshot
Design of Univac®-LARC system
inferredcites →https://doi.org/10.1145/1463891.1463945openalex-snapshot
Circuit implementation of high-speed pipeline systems
inferredcites →https://doi.org/10.1145/1464039.1464045openalex-snapshot
Parallel operation in the control data 6600
inferredcites →https://doi.org/10.1145/146628.139709openalex-snapshot
Alternative implementations of two-level adaptive branch prediction
inferredcites →https://doi.org/10.1145/1476793.1476883openalex-snapshot
Maximum-rate pipeline systems
inferredcites →https://doi.org/10.1145/1478559.1478561openalex-snapshot
A survey of techniques for recognizing parallel processable streams in computer programs
inferredcites →https://doi.org/10.1145/17356.17391openalex-snapshot
HPSm, a high performance restricted data flow architecture having minimal functionality
inferredcites →https://doi.org/10.1145/17356.17401openalex-snapshot
Highly concurrent scalar processing
inferredcites →https://doi.org/10.1145/17356.17403openalex-snapshot
Optimal pipelining in supercomputers
inferredcites →https://doi.org/10.1145/18906.18924openalex-snapshot
Some experiments in global microcode compaction
inferredcites →https://doi.org/10.1145/18927.18924openalex-snapshot
Some experiments in global microcode compaction
inferredcites →https://doi.org/10.1145/19530.19541openalex-snapshot
URPR—An extension of URCR for software pipelining
inferredcites →https://doi.org/10.1145/2166.357217openalex-snapshot
Postpass Code Optimization of Pipeline Constraints
inferredcites →https://doi.org/10.1145/2465.2468openalex-snapshot
The Manchester prototype dataflow computer
inferredcites →https://doi.org/10.1145/255305.255322openalex-snapshot
GURPR---a method for global software pipelining
inferredcites →https://doi.org/10.1145/2591635.2667158openalex-snapshot
Code scheduling and register allocation in large basic blocks
inferredcites →https://doi.org/10.1145/2591635.2667160openalex-snapshot
Aglobalresource-constrained parallelization technique
inferredcites →https://doi.org/10.1145/285930.285973openalex-snapshot
Improving the throughput of a pipeline by insertion of delays
inferredcites →https://doi.org/10.1145/285930.285980openalex-snapshot
A study of branch prediction strategies
inferredcites →https://doi.org/10.1145/285930.285985openalex-snapshot
Very long instruction work architectures and the ELI-512
inferredcites →https://doi.org/10.1145/285930.285989openalex-snapshot
HPSm, a high performance restricted data flow architecture having minimal functionality
inferredcites →https://doi.org/10.1145/285930.285992openalex-snapshot
Instruction issue logic for high-performance, interruptable pipelined processors
inferredcites →https://doi.org/10.1145/30350.30353openalex-snapshot
Checkpoint repair for out-of-order execution machines
inferredcites →https://doi.org/10.1145/30350.30354openalex-snapshot
Instruction issue logic for high-performance, interruptable pipelined processors
inferredcites →https://doi.org/10.1145/321607.321620openalex-snapshot
The Generation of Optimal Code for Arithmetic Expressions
inferredcites →https://doi.org/10.1145/321958.321970openalex-snapshot
Optimal Code Generation for Expression Trees
inferredcites →https://doi.org/10.1145/321958.321971openalex-snapshot
Code Generation for a One-Register Machine
inferredcites →https://doi.org/10.1145/321992.322001openalex-snapshot
Code Generation for Expressions with Common Subexpressions
inferredcites →https://doi.org/10.1145/325096.325160openalex-snapshot
Boosting beyond static scheduling in a superscalar processor
inferredcites →https://doi.org/10.1145/356698.356700openalex-snapshot
Deterministic Processor Scheduling
inferredcites →https://doi.org/10.1145/356819.356822openalex-snapshot
Local Microcode Compaction Techniques
inferredcites →https://doi.org/10.1145/361604.361619openalex-snapshot
A comparison of list schedules for parallel processing systems
inferredcites →https://doi.org/10.1145/36204.36191openalex-snapshot
A study of scalar compilation techniques for pipelined supercomputers
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/384281.808217openalex-snapshot
An improvement of trace scheduling for global microcode compaction
inferredcites →https://doi.org/10.1145/502874.502879openalex-snapshot
A Fortran compiler for the FPS-164 scientific computer
inferredcites →https://doi.org/10.1145/502874.502896openalex-snapshot
Register allocation by priority-based coloring
inferredcites →https://doi.org/10.1145/512950.512953openalex-snapshot
Code-generation for machines with multiregister operations
inferredcites →https://doi.org/10.1145/55364.55407openalex-snapshot
Code scheduling and register allocation in large basic blocks
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1145/633615.810654openalex-snapshot
The microprogramming of pipelined processors
inferredcites →https://doi.org/10.1145/633625.52406openalex-snapshot
Exploiting parallel microprocessor microarchitectures with a compiler code generator
inferredcites →https://doi.org/10.1145/633642.803972openalex-snapshot
Maximal rate pipelined solutions to recurrence problems
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/70082.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/74925.74951openalex-snapshot
Comparing software and hardware schemes for reducing the cost of branches
inferredcites →https://doi.org/10.1145/74926.74951openalex-snapshot
Comparing software and hardware schemes for reducing the cost of branches
inferredcites →https://doi.org/10.1145/773453.808172openalex-snapshot
Instruction issue logic for pipelined supercomputers
inferredcites →https://doi.org/10.1145/79505.79508openalex-snapshot
A study of scalar compilation techniques for pipelined supercomputers
inferredcites →https://doi.org/10.1145/800015.808172openalex-snapshot
Instruction issue logic for pipelined supercomputers
inferredcites →https://doi.org/10.1145/800050.801820openalex-snapshot
Hardware/software tradeoffs for increased performance
inferredcites →https://doi.org/10.1145/800050.801821openalex-snapshot
Coding guidelines for pipelined processors
inferredcites →https://doi.org/10.1145/800050.801832openalex-snapshot
Architectural support for the efficient generation of code for horizontal architectures
inferredcites →https://doi.org/10.1145/800110.803575openalex-snapshot
Improving the throughput of a pipeline by insertion of delays
inferredcites →https://doi.org/10.1145/800118.803846openalex-snapshot
An approach to optimization of horizontal microprograms
inferredcites →https://doi.org/10.1145/800118.803848openalex-snapshot
On storage optimization of horizontal microprograms
inferredcites →https://doi.org/10.1145/800118.803849openalex-snapshot
A representation for the analysis of microprogram operation
inferredcites →https://doi.org/10.1145/800148.804855openalex-snapshot
A Control Word Model for detecting conflicts between microprograms
inferredcites →https://doi.org/10.1145/800230.806977openalex-snapshot
An overview of the PL.8 compiler
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/800255.810654openalex-snapshot
The microprogramming of pipelined processors
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/88616.88621openalex-snapshot
The priority-based coloring approach to register allocation
inferredcites →https://doi.org/10.1145/93542.93553openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/989393.989413openalex-snapshot
Efficient instruction scheduling for a pipelined architecture
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1147/rd.11.0008openalex-snapshot
Design of Logic for Recognition of Printed Characters by Simulation
inferredcites →https://doi.org/10.1147/rd.111.0008openalex-snapshot
The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling
inferredcites →https://doi.org/10.1147/rd.111.0025openalex-snapshot
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
inferredcites →https://doi.org/10.1147/rd.182.0138openalex-snapshot
Parallel Solution of Recurrence Problems
inferredcites →https://doi.org/10.1147/rd.341.0037openalex-snapshot
Machine organization of the IBM RISC System/6000 processor
inferredcites →https://doi.org/10.1147/rd.341.0085openalex-snapshot
Instruction scheduling for the IBM RISC System/6000 processor
inferredcites →https://doi.org/10.1147/rd.341.0093openalex-snapshot
Instruction scheduling beyond basic blocks
inferredcites →https://doi.org/10.1147/sj.82.0118openalex-snapshot
An auxiliary processing system for array calculations
inferredcites →https://doi.org/10.1201/9781315219271-6openalex-snapshot
Introduction to computer architecture
inferredcites →https://doi.org/10.1287/opre.9.6.841openalex-snapshot
Parallel Sequencing and Assembly Line Problems
inferredcites →https://doi.org/10.2172/5752434openalex-snapshot
Optimization of horizontal microcode within and beyond basic blocks: an application of processor scheduling with resources
inferredcites →https://doi.org/10.2307/3009192openalex-snapshot
Introduction to Sequencing and Scheduling
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Building a retargetable local instruction scheduler
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A code compression system based on pipelined interpreters
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Parallelizing and Vectorizing Compilers
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Classification and generation of schedules for VLIW processors
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Pragmatic integrated scheduling for clustered VLIW architectures
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A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards
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Hardware Support for Multithreaded Execution of Loops with Limited Parallelism
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A Static Data Dependence Analysis Approach for Software Pipelining
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A Dynamic Data Dependence Analysis Approach for Software Pipelining
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Computer Assisted Source-Code Parallelisation
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Multi-dimensional Kernel Generation for Loop Nest Software Pipelining
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Comparison of two common pipeline structures
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Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture
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Java Virtual Machine performance analysis with Java instruction level parallelism and advanced folding scheme
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Efficient pipelining of nested loops: unroll-and-squash
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OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS
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Minimum register requirements for a modulo schedule
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Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution
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