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Cache tiling for high performance morphological image processing

https://doi.org/10.1007/bf01212412
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf00158166openalex-snapshot
The image understanding architecture
inferredcites →https://doi.org/10.1007/bf01212310openalex-snapshot
Pipeline architectures for morphologie image analysis
inferredcites →https://doi.org/10.1016/0141-9331(85)90187-5openalex-snapshot
Computer architecture and parallel processing
inferredcites →https://doi.org/10.1016/0734-189x(89)90041-8openalex-snapshot
Fundamentals of digital image processing
inferredcites →https://doi.org/10.1109/38.50676openalex-snapshot
The truth about texture mapping
inferredcites →https://doi.org/10.1109/38.55156openalex-snapshot
Jim Blinn's corner-wonderful world of video (animation)
inferredcites →https://doi.org/10.1109/icpr.1990.119431openalex-snapshot
An object-oriented language for image and vision execution (OLIVE)
inferredcites →https://doi.org/10.1109/icpr.1990.119434openalex-snapshot
The VIEW-Station environment: tools and architecture for a platform-independent image-processing workstation
inferredcites →https://doi.org/10.1109/ipps.1991.153793openalex-snapshot
Proteus system architecture and organization
inferredcites →https://doi.org/10.1109/tc.1980.1675684openalex-snapshot
Design of a Massively Parallel Processor
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/800053.801935openalex-snapshot
The cytocomputer

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9781119751991.ch10openalex-snapshot
The Theoretical and Technological Peculiarities of Aerospace Imagery Processing and Interpretation By Means of Artificial Neural Networks
inferred← citeshttps://doi.org/10.1002/cpe.4375openalex-snapshot
Tile/line access cache memory based on a multi‐level Z‐order tiling data layout
inferred← citeshttps://doi.org/10.1006/jpdc.1995.1040openalex-snapshot
2D and 3D Optimal Parallel Image Warping
inferred← citeshttps://doi.org/10.1007/bf01213474openalex-snapshot
Proteus: A reconfigurable computational network for computer vision
inferred← citeshttps://doi.org/10.1016/s0098-3004(97)00033-2openalex-snapshot
Virtual-memory tiling for spatial data handling in GIS
inferred← citeshttps://doi.org/10.1016/s0165-1684(97)00041-8openalex-snapshot
Optimal cache usage for separable image processing algorithms on general purpose workstations
inferred← citeshttps://doi.org/10.1109/71.995819openalex-snapshot
Systolic opportunities for multidimensional data streams
inferred← citeshttps://doi.org/10.1109/hpcsim.2016.7568425openalex-snapshot
A cache memory with unit tile and line accessibility
inferred← citeshttps://doi.org/10.1109/icis.2016.7550744openalex-snapshot
A cache memory with unit tile and line accessibility
inferred← citeshttps://doi.org/10.1109/icpr.1992.202128openalex-snapshot
Proteus: a reconfigurable computational network for computer vision
inferred← citeshttps://doi.org/10.1109/prs.1993.586086openalex-snapshot
Permutation warping for data parallel volume rendering
inferred← citeshttps://doi.org/10.1117/12.216369openalex-snapshot
Tiling and demand-driven evaluation for picture processing
inferred← citeshttps://doi.org/10.1145/166181.166189openalex-snapshot
Permutation warping for data parallel volume rendering
inferred← citeshttps://doi.org/10.1155/2019/9601961openalex-snapshot
Design and Implementation of Cache Memory with Dual Unit Tile/Line Accessibility
inferred← citeshttps://doi.org/10.31274/rtd-180813-13230openalex-snapshot
Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)
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