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Data-parallel C on a reconfigurable logic array

https://doi.org/10.1007/bf01212873
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3966-7_4openalex-snapshot
The IBM High-Level Synthesis System
inferredcites →https://doi.org/10.1007/bfb0116397openalex-snapshot
The Connection Machine
inferredcites →https://doi.org/10.1038/scientificamerican0687-108openalex-snapshot
The Connection Machine
inferredcites →https://doi.org/10.1109/2.204677openalex-snapshot
Processor reconfiguration through instruction-set metamorphosis
inferredcites →https://doi.org/10.1109/2.375174openalex-snapshot
Processing in memory: the Terasys massively parallel PIM array
inferredcites →https://doi.org/10.1109/2.67197openalex-snapshot
Building and using a highly parallel programmable logic array
inferredcites →https://doi.org/10.1109/fmpc.1995.380448openalex-snapshot
A data parallel C and its platforms
inferredcites →https://doi.org/10.1109/fpga.1993.279464openalex-snapshot
Searching genetic databases on Splash 2
inferredcites →https://doi.org/10.1109/fpga.1993.279483openalex-snapshot
Spyder: a reconfigurable VLIW processor using FPGAs
inferredcites →https://doi.org/10.1109/fpga.1994.315599openalex-snapshot
PAM programming environments: practice and experience
inferredcites →https://doi.org/10.1109/fpga.1994.315603openalex-snapshot
Global control synthesis for an MIMD/FPGA machine
inferredcites →https://doi.org/10.1109/fpga.1994.315606openalex-snapshot
An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-60294-1_134openalex-snapshot
Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays
inferred← citeshttps://doi.org/10.1007/bfb0055252openalex-snapshot
Instruction-level parallelism for reconfigurable computing
inferred← citeshttps://doi.org/10.1016/b978-012370522-8.50015-7openalex-snapshot
Programming Data Parallel FPGA Applications Using the SIMD/Vector Model
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.10.006openalex-snapshot
SIMD architecture on FPGA for scientific computing aboard a space instrument
inferred← citeshttps://doi.org/10.1109/2.375174openalex-snapshot
Processing in memory: the Terasys massively parallel PIM array
inferred← citeshttps://doi.org/10.1109/fccm.2007.55openalex-snapshot
Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1109/fccm.2007.62openalex-snapshot
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
inferred← citeshttps://doi.org/10.1109/fccm.2009.37openalex-snapshot
Application Experiments: MPPA and FPGA
inferred← citeshttps://doi.org/10.1109/fmpc.1995.380448openalex-snapshot
A data parallel C and its platforms
inferred← citeshttps://doi.org/10.1109/fpga.1997.624619openalex-snapshot
Automated target recognition on SPLASH 2
inferred← citeshttps://doi.org/10.1109/fpga.1999.803669openalex-snapshot
Parallelizing applications into silicon
inferred← citeshttps://doi.org/10.1109/fpga.2000.903396openalex-snapshot
Automatic synthesis of data storage and control structures for FPGA-based computing engines
inferred← citeshttps://doi.org/10.1109/fpga.2000.903440openalex-snapshot
A C to hardware/software compiler
inferred← citeshttps://doi.org/10.1109/hicss.1999.772878openalex-snapshot
An overview of advances in reconfigurable computing systems
inferred← citeshttps://doi.org/10.1109/ipdps.2005.121openalex-snapshot
Bandwidth Management with a Reconfigurable Data Cache
inferred← citeshttps://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferred← citeshttps://doi.org/10.1109/micro.2005.17openalex-snapshot
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
inferred← citeshttps://doi.org/10.1145/1176254.1176322openalex-snapshot
Increasing hardware efficiency with multifunction loop accelerators
inferred← citeshttps://doi.org/10.1145/360276.360322openalex-snapshot
Attacking the semantic gap between application programming languages and configurable hardware
inferred← citeshttps://doi.org/10.1145/360276.360324openalex-snapshot
Matching and searching analysis for parallel hardware implementation on FPGAs
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