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Instruction-level parallelism for reconfigurable computing

https://doi.org/10.1007/bfb0055252
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf01212873openalex-snapshot
Data-parallel C on a reconfigurable logic array
inferredcites →https://doi.org/10.1109/2.546613openalex-snapshot
Maximizing multiprocessor performance with the SUIF compiler
inferredcites →https://doi.org/10.1109/2.683004openalex-snapshot
Hardware compilation: translating programs into circuits
inferredcites →https://doi.org/10.1109/fpga.1993.279476openalex-snapshot
A data-parallel programming model for reconfigurable architectures
inferredcites →https://doi.org/10.1109/fpga.1994.315596openalex-snapshot
DPGA-coupled microprocessors: commodity ICs for the early 21st Century
inferredcites →https://doi.org/10.1109/fpga.1994.315606openalex-snapshot
An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs
inferredcites →https://doi.org/10.1109/fpga.1994.315611openalex-snapshot
Density enhancement of a neural network using FPGAs and run-time reconfiguration
inferredcites →https://doi.org/10.1109/fpga.1997.624600openalex-snapshot
Garp: a MIPS processor with a reconfigurable coprocessor
inferredcites →https://doi.org/10.1126/science.253.5025.1233openalex-snapshot
Instruction-Level Parallel Processing
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/223982.225965openalex-snapshot
A comparison of full and partial predicated execution support for ILP processors
inferredcites →https://doi.org/10.1145/225830.225965openalex-snapshot
A comparison of full and partial predicated execution support for ILP processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Morphware and Configware
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A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
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StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
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Factors Influencing the Performance of a CPU-RFU Hybrid Architecture
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A Coarse-Grain Dynamically Reconfigurable System and Compilation Framework
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Co-Synthesis to a Hybrid RISC/FPGA Architecture
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Application of Reconfigurable CORDIC Architectures
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Hardware Implementation Techniques for Recursive Calls and Loops
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Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture
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Field-Programmable Logic and Applications From FPGAs to Computing Paradigm
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Stream computations organized for reconfigurable execution
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Modern development methods and tools for embedded reconfigurable systems: A survey
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Co-Synthesis to a Hybrid RISC/FPGA Architecture
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Application of Reconfigurable CORDIC Architectures
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The Universal Configurable Block/Machine— An Approach for a Configurable SoC-Architecture
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The Garp architecture and C compiler
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Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C
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Pipeline vectorization
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Adaptive multiuser online reconfigurable engine
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Automatic compilation of loops to exploit operator parallelism on configurable arithmetic logic units
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A formal approach to context scheduling for multicontext reconfigurable architectures
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A framework for reconfigurable computing: task scheduling and context management
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Reconfigurable computing based on universal configurable blocks-a new approach for supporting performance- and realtime-dominated applications
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Coarse grain reconfigurable architectures
inferred← citeshttps://doi.org/10.1109/aspdac.2002.994945openalex-snapshot
Software pipelining for coarse-grained reconfigurable instruction set processors
inferred← citeshttps://doi.org/10.1109/dac.2002.1012646openalex-snapshot
Exploiting operation level parallelism through dynamically reconfigurable datapaths
inferred← citeshttps://doi.org/10.1109/dac.2003.1219090openalex-snapshot
Global resource sharing for synthesis of control data flow graphs on FPGAs
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A decade of reconfigurable computing: a visionary retrospective
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Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
inferred← citeshttps://doi.org/10.1109/dsd.2001.952125openalex-snapshot
Reconfigurable computing: a new business model-and its impact on SoC design
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Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs
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Exploiting Memory-Level Parallelism in Reconfigurable Accelerators
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StReAm: object-oriented programming of stream architectures using PAM-Blox
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Peer-to-peer hardware-software interfaces for reconfigurable fabrics
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Kernel formation in Garpcc
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Virtualization on the Tartan Reconfigurable Architecture
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An Automatic Compilation Framework for Configurable Architectures
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DRESC: a retargetable compiler for coarse-grained reconfigurable architectures
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Trends in reconfigurable logic and reconfigurable computing
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Efficient pipelining of nested loops: unroll-and-squash
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Overlapping memory operations with circuit evaluation in reconfigurable computing
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SOFF: An OpenCL High-Level Synthesis Framework for FPGAs
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Reconfigurable computing systems
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Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques
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Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures
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Reconfigurable instruction set processors from a hardware/software perspective
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Spatial computation
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Spatial computation
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Spatial computation
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Code transformation strategies for extensible embedded processors
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Compiling for reconfigurable computing
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Hardware-software co-design of embedded reconfigurable architectures
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Attacking the semantic gap between application programming languages and configurable hardware
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A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
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Exploiting operation level parallelism through dynamically reconfigurable datapaths
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Global resource sharing for synthesis of control data flow graphs on FPGAs
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Automatic compilation to a coarse-grained reconfigurable system-opn-chip
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Architectural trade-offs in dynamically reconfigurable processors
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Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
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Efficient Implementation of Fast Fourier Transform Using NOC
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