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The implicit set paradigm: A new approach to finite state system verification
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/inco.1995.1055openalex-snapshot
Testing Language Containment for ω-Automata Using BDDs
inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot
Verification of synchronous sequential machines based on symbolic execution
inferredcites →https://doi.org/10.1007/3-540-55179-4_20openalex-snapshot
Generating BDDs for symbolic model checking in CCS
inferredcites →https://doi.org/10.1007/3-540-55179-4_21openalex-snapshot
Vectorized symbolic model checking of computation tree logic for sequential machine verification
inferredcites →https://doi.org/10.1007/3-540-56496-9_9openalex-snapshot
Symbolic bisimulation minimisation
inferredcites →https://doi.org/10.1007/978-1-4471-3544-9_17openalex-snapshot
Using the Declarative Language LUSTRE for Circuit Verification
inferredcites →https://doi.org/10.1007/978-1-4615-0292-0_4openalex-snapshot
A Unified Framework for the Formal Verification of Sequential Circuits
inferredcites →https://doi.org/10.1007/bf00265555openalex-snapshot
Fairness and related properties in transition systems ? a temporal logic to deal with fairness
inferredcites →https://doi.org/10.1007/bfb0023716openalex-snapshot
Verifying temporal properties of sequential machines without building their state diagrams
inferredcites →https://doi.org/10.1016/0096-0551(80)90011-9openalex-snapshot
Introduction to automata theory, languages, and computation
inferredcites →https://doi.org/10.1016/0378-4754(81)90068-9openalex-snapshot
Introduction to automata theory, languages and computation
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1016/b978-0-444-88074-1.50021-4openalex-snapshot
Temporal and Modal Logic
inferredcites →https://doi.org/10.1090/dimacs/003/07openalex-snapshot
Verifying temporal properties of sequential machines without building their state diagrams
inferredcites →https://doi.org/10.1090/dimacs/003/20openalex-snapshot
A computation theory and implementation of sequential hardware equivalence
inferredcites →https://doi.org/10.1109/12.53586openalex-snapshot
Finding the optimal variable ordering for binary decision diagrams
inferredcites →https://doi.org/10.1109/12.73590openalex-snapshot
On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication
inferredcites →https://doi.org/10.1109/43.251158openalex-snapshot
Verification of relations between synchronous machines
inferredcites →https://doi.org/10.1109/43.3210openalex-snapshot
On the verification of sequential machines at differing levels of abstraction
inferredcites →https://doi.org/10.1109/5.97300openalex-snapshot
The synchronous data flow programming language LUSTRE
inferredcites →https://doi.org/10.1109/cicc.1991.164034openalex-snapshot
Improving BDDs manipulation through incremental reduction and enhanced heuristics
inferredcites →https://doi.org/10.1109/dac.1986.1586089openalex-snapshot
A New Method for Verifying Sequential Circuits
inferredcites →https://doi.org/10.1109/iccad.1988.122450openalex-snapshot
Evaluation and improvement of Boolean comparison method based on binary decision diagrams
inferredcites →https://doi.org/10.1109/iccad.1988.122451openalex-snapshot
Logic verification using binary decision diagrams in a logic synthesis environment
inferredcites →https://doi.org/10.1109/iccad.1990.129860openalex-snapshot
Implicit state enumeration of finite state machines using BDD's
inferredcites →https://doi.org/10.1109/iccad.1990.129940openalex-snapshot
Don't care minimization of multi-level sequential logic networks
inferredcites →https://doi.org/10.1109/iccad.1991.185307openalex-snapshot
Minimization of binary decision diagrams based on exchanges of variables
inferredcites →https://doi.org/10.1109/iccd.1989.63394openalex-snapshot
Ordered binary decision diagrams and circuit structure
inferredcites →https://doi.org/10.1109/iccd.1990.130210openalex-snapshot
New ideas on symbolic manipulations of finite state machines
inferredcites →https://doi.org/10.1109/iscas.1991.176226openalex-snapshot
Incremental reduction of binary decision diagrams
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/123041.123062openalex-snapshot
Programming and verifying critical systems by means of the synchronous data-flow language LUSTRE
inferredcites →https://doi.org/10.1145/123186.123222openalex-snapshot
Efficient implementation of a BDD package
inferredcites →https://doi.org/10.1145/123186.123223openalex-snapshot
Sequential circuit verification using symbolic model checking
inferredcites →https://doi.org/10.1145/123186.123225openalex-snapshot
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
inferredcites →https://doi.org/10.1145/125083.123062openalex-snapshot
Programming and verifying critical systems by means of the synchronous data-flow language LUSTRE
inferredcites →https://doi.org/10.1145/127601.127701openalex-snapshot
Formal hardware verification by symbolic ternary trajectory evaluation
inferredcites →https://doi.org/10.1145/127601.127702openalex-snapshot
Representing circuits more efficiently in symbolic model checking
inferredcites →https://doi.org/10.1145/127601.127705openalex-snapshot
Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams
inferredcites →https://doi.org/10.1145/5397.5399openalex-snapshot
Automatic verification of finite-state concurrent systems using temporal logic specifications
inferredcites →https://doi.org/10.1146/annurev.cs.02.060187.001413openalex-snapshot
Research on Automatic Verification of Finite-State Concurrent Systems
inferredcites →https://doi.org/10.5555/113938.149645openalex-snapshot
Exact calculation of synchronization sequences based on binary decision diagrams
inferredcites →https://doi.org/10.5555/285730.285764openalex-snapshot
Proving circuit correctness using formal comparison between expected and extracted behaviour
inferredcites →https://doi.org/10.5555/318013.318045openalex-snapshot
A New Method for Verifying Sequential Circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-36383-1_7openalex-snapshot
Algorithms and Heuristics in VLSI Design
inferred← citeshttps://doi.org/10.1007/3-540-45506-x_6openalex-snapshot
Data Structures for Boolean Functions BDDs — Foundations and Applications
inferred← citeshttps://doi.org/10.1007/978-1-4615-0817-5_11openalex-snapshot
Ordered Binary Decision Diagrams
inferred← citeshttps://doi.org/10.1007/978-3-642-12805-9_4openalex-snapshot
A Model for Integrating Dialogue and the Execution of Joint Plans
inferred← citeshttps://doi.org/10.1007/978-3-642-21940-5_16openalex-snapshot
Computing Argumentation in Polynomial Number of BDD Operations: A Preliminary Report
inferred← citeshttps://doi.org/10.1007/978-3-642-60831-5_39openalex-snapshot
Geordnete binäre Entscheidungsgraphen und ihre Bedeutung im rechnergestutzten Entwurf hochintegrierter Schaltkreise
inferred← citeshttps://doi.org/10.1007/bfb0029984openalex-snapshot
On the influence of the state encoding on OBDD-representations of finite state machines
inferred← citeshttps://doi.org/10.1051/ita:1999103openalex-snapshot
On the Influence of the State Encoding on OBDD-Representations of Finite State Machines
inferred← citeshttps://doi.org/10.1142/s0218126699000165openalex-snapshot
ORDERED BINARY DECISION DIAGRAMS AND THEIR SIGNIFICANCE IN COMPUTER-AIDED DESIGN OF VLSI CIRCUITS
inferred← citeshttps://doi.org/10.1145/774572.774573openalex-snapshot
Comprehensive frequency-dependent substrate noise analysis using boundary element methods
inferred← citeshttps://doi.org/10.14288/1.0051407openalex-snapshot
Compositional model checking of partially ordered state spaces
inferred← citeshttps://doi.org/10.5555/603095.603174openalex-snapshot
Color permutation: an iterative algorithm for memory packing
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