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Verifying temporal properties of sequential machines without building their state diagrams

https://doi.org/10.1007/bfb0023716
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot
Verification of synchronous sequential machines based on symbolic execution
inferredcites →https://doi.org/10.1007/bf00265555openalex-snapshot
Fairness and related properties in transition systems ? a temporal logic to deal with fairness
inferredcites →https://doi.org/10.1017/cbo9780511816239openalex-snapshot
Switching and Finite Automata Theory
inferredcites →https://doi.org/10.1109/edac.1990.136620openalex-snapshot
Formal Boolean manipulations for the verification of sequential machines
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/123186.123223openalex-snapshot
Sequential circuit verification using symbolic model checking
inferredcites →https://doi.org/10.1146/annurev.cs.02.060187.001413openalex-snapshot
Research on Automatic Verification of Finite-State Concurrent Systems
inferredcites →https://doi.org/10.5555/949970.949984openalex-snapshot
Formal Boolean manipulations for the verification of sequential machines

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Formal Methods for Functional Verification
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