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The torus routing chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Virtual cut-through: A new computer communication switching technique
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Concurrent VLSI Architectures
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Synchronizing Large VLSI Processor Arrays
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Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
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Prevention of Deadlocks in Packet-Switched Data Transport Systems
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The extension of object-oriented languages to a homogeneous, concurrent architecture
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Placement of Communicating Processes on Multiprocessor Networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
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The t/k-diagnosability of m-ary n-cube networks
inferred← citeshttps://doi.org/10.1016/j.vlsi.2004.03.006openalex-snapshot
Cost considerations in network on chip
inferred← citeshttps://doi.org/10.1016/j.vlsi.2014.10.006openalex-snapshot
High Throughput Asynchronous NoC Design under High Process Variation
inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.06.014openalex-snapshot
FRDS: An efficient unique on-Chip interconnection network architecture
inferred← citeshttps://doi.org/10.1016/s0020-0190(02)00477-5openalex-snapshot
Fault-tolerant wormhole routing for hypercube networks
inferred← citeshttps://doi.org/10.1016/s0026-2714(96)00297-1openalex-snapshot
A fault-tolerant communications switch prototype
inferred← citeshttps://doi.org/10.1016/s0045-7906(96)00010-9openalex-snapshot
Material identification algorithms for parallel systems
inferred← citeshttps://doi.org/10.1016/s0141-9331(98)00043-xopenalex-snapshot
Performance/cost analyses for common network topologies
inferred← citeshttps://doi.org/10.1016/s0166-218x(99)00106-7openalex-snapshot
A family of Cayley graphs on the hexavalent grid
inferred← citeshttps://doi.org/10.1016/s0166-5316(01)00058-xopenalex-snapshot
Modeling of interconnection subsystems for massively parallel computers
inferred← citeshttps://doi.org/10.1016/s0167-739x(00)00082-0openalex-snapshot
A new-generation parallel computer and its performance evaluation
inferred← citeshttps://doi.org/10.1016/s0167-8191(01)00116-8openalex-snapshot
Wormhole routing for torus networks with faults
inferred← citeshttps://doi.org/10.1016/s0167-8191(02)00110-2openalex-snapshot
A vision-application adaptable computer concept and its implementation in FreeTIV computer
inferred← citeshttps://doi.org/10.1016/s0167-8191(98)00009-xopenalex-snapshot
Unicast-based multicast algorithm in wormhole-routed star graph interconnection networks
inferred← citeshttps://doi.org/10.1016/s0167-8191(99)00073-3openalex-snapshot
Performance evaluation of parallel systems
inferred← citeshttps://doi.org/10.1016/s0167-8191(99)00113-1openalex-snapshot
A fault-tolerant routing algorithm for wormhole routed meshes
inferred← citeshttps://doi.org/10.1016/s0928-4869(97)00031-1openalex-snapshot
A concurrent network architecture for cost-efficient parallel computing using workstation clusters
inferred← citeshttps://doi.org/10.1016/s1383-7621(00)00010-2openalex-snapshot
YOMNA – An efficient deadlock-free multicast wormhole algorithm in 2-D mesh multicomputers
inferred← citeshttps://doi.org/10.1016/s1383-7621(97)00019-2openalex-snapshot
A cost-effective methodology for the evaluation of interconnection networks
inferred← citeshttps://doi.org/10.1016/s1383-7621(97)00037-4openalex-snapshot
Advanced workstation cluster architectures for parallel computing
inferred← citeshttps://doi.org/10.1016/s1383-7621(99)00048-xopenalex-snapshot
Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors
inferred← citeshttps://doi.org/10.1023/a:1008155920176openalex-snapshot
Wormhole Broadcast in Hypercubes
inferred← citeshttps://doi.org/10.1023/a:1008160800606openalex-snapshot
The Multi-Level Communication: Efficient Routing for Interconnection Networks
inferred← citeshttps://doi.org/10.1023/b:supe.0000032806.83812.fbopenalex-snapshot
Heuristic Contention-Free Broadcast in Heterogeneous Networks of Workstations with Multiple Send and Receive Speeds
inferred← citeshttps://doi.org/10.1049/iet-cdt.2013.0012openalex-snapshot
Prevention slot flow‐control mechanism for low latency torus network‐on‐chip
inferred← citeshttps://doi.org/10.1049/iet-cdt.2018.5154openalex-snapshot
DICA: destination intensity and congestion‐aware output selection strategy for network‐on‐chip systems
inferred← citeshttps://doi.org/10.1049/iet-cdt:20050068openalex-snapshot
Admitting and ejecting flits in wormhole-switched networks on chip
inferred← citeshttps://doi.org/10.1049/ip-cdt:20030062openalex-snapshot
Fault-tolerant wormhole routing in torus networks with overlapped block faults
inferred← citeshttps://doi.org/10.1049/ip-cdt:20045092openalex-snapshot
Communication and task scheduling of application-specific networks-on-chip
inferred← citeshttps://doi.org/10.1049/ip-cdt:20050067openalex-snapshot
Implementation of guaranteed services in the MANGO clockless network-on-chip
inferred← citeshttps://doi.org/10.1049/ip-sen:20030134openalex-snapshot
Configuration discovery and mapping of a home network
inferred← citeshttps://doi.org/10.1049/joe.2013.0209openalex-snapshot
Wireless network‐on‐chip: a survey
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