On the public citation graph

Using FPGAs to implement self-timed systems

0 signed · 50 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf01660031openalex-snapshot

The torus routing chip

inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot

A formal model for defining and classifying delay-insensitive circuits and systems

inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot

Compiling communicating processes into delay-insensitive VLSI circuits

inferredcites →https://doi.org/10.1109/12.123377openalex-snapshot

An efficient implementation of Boolean functions as self-timed circuits

inferredcites →https://doi.org/10.1109/12.2252openalex-snapshot

Q-modules: internally clocked delay-insensitive modules

inferredcites →https://doi.org/10.1109/4.18600openalex-snapshot

An architecture for electrically configurable gate arrays

inferredcites →https://doi.org/10.1109/icassp.1989.266983openalex-snapshot

Design of clock-free asynchronous systems for real-time signal processing

inferredcites →https://doi.org/10.1109/iccad.1989.76949openalex-snapshot

Translating concurrent programs into delay-insensitive circuits

inferredcites →https://doi.org/10.1109/iccd.1988.25680openalex-snapshot

VLSI programming and silicon compilation-a novel approach from Philips research

inferredcites →https://doi.org/10.1142/9467openalex-snapshot

Computer Arithmetic

inferredcites →https://doi.org/10.1145/63526.63532openalex-snapshot

Micropipelines

inferredcites →https://doi.org/10.1145/77254.77262openalex-snapshot

An efficient implementation of Boolean functions nd finite state machine as self-timed circuit

inferredcites →https://doi.org/10.1184/r1/6587345openalex-snapshot

A delay insensitive regular expression recognizer

inferredcites →https://doi.org/10.21236/ada188621openalex-snapshot

Parts-R-Us.

inferredcites →https://doi.org/10.21236/ada447033openalex-snapshot

Syntax-Directed Translation of Concurrent Programs into Self-Timed Circuits

inferredcites →https://doi.org/10.7907/j438-dz84openalex-snapshot

Automated Compilation of Concurrent Programs into Self-Timed Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-46117-5_6openalex-snapshot

Implementing Asynchronous Circuits on LUT Based FPGAs

inferred← citeshttps://doi.org/10.1007/3-540-60294-1_112openalex-snapshot

Compiling Ruby into FPGAs

inferred← citeshttps://doi.org/10.1007/3-540-60294-1_95openalex-snapshot

Self-timed FPGA systems

inferred← citeshttps://doi.org/10.1007/978-3-540-45234-8_35openalex-snapshot

Globally Asynchronous Locally Synchronous FPGA Architectures

inferred← citeshttps://doi.org/10.1007/s10470-020-01602-3openalex-snapshot

Detailed implementation of asynchronous circuits on commercial FPGAs

inferred← citeshttps://doi.org/10.1016/j.vlsi.2017.05.002openalex-snapshot

Simple method of asynchronous circuits implementation in commercial FPGAs

inferred← citeshttps://doi.org/10.1049/ip-cdt:19960655openalex-snapshot

Asynchronous FPGA architectures

inferred← citeshttps://doi.org/10.1109/91.554446openalex-snapshot

The synthesis of compact fuzzy neural circuits

inferred← citeshttps://doi.org/10.1109/92.475968openalex-snapshot

The Triptych FPGA architecture

inferred← citeshttps://doi.org/10.1109/92.748198openalex-snapshot

Peephole optimization of asynchronous macromodule networks

inferred← citeshttps://doi.org/10.1109/acsd.2008.4574603openalex-snapshot

Asynchronous pipeline controller based on early acknowledgement protocol

inferred← citeshttps://doi.org/10.1109/andescon.2010.5633258openalex-snapshot

FPGA implementation of asynchronous controllers from generalized multi-burst graph specification

inferred← citeshttps://doi.org/10.1109/arvlsi.1995.515612openalex-snapshot

Low latency self-timed flow-through FIFOs

inferred← citeshttps://doi.org/10.1109/asic.1999.806530openalex-snapshot

A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing

inferred← citeshttps://doi.org/10.1109/atc.2009.5349341openalex-snapshot

New approaches to design asynchronous circuits on FPGAs

inferred← citeshttps://doi.org/10.1109/cicc.1994.379761openalex-snapshot

Using FPGAs to prototype a self-timed floating point co-processor

inferred← citeshttps://doi.org/10.1109/cicc.1996.510531openalex-snapshot

A self clocked FPGA for general purpose logic emulation

inferred← citeshttps://doi.org/10.1109/delta.2010.40openalex-snapshot

Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA

inferred← citeshttps://doi.org/10.1109/dsd.2014.85openalex-snapshot

Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGA

inferred← citeshttps://doi.org/10.1109/eh.2001.937963openalex-snapshot

Asynchronous embryonics

inferred← citeshttps://doi.org/10.1109/etlpds.1996.508879openalex-snapshot

Proceedings of 18th Annual Electrical Overstress/Electrostatic Discharge Symposium

inferred← citeshttps://doi.org/10.1109/hicss.1993.270625openalex-snapshot

Specification, simulation, and synthesis of self-timed circuits

inferred← citeshttps://doi.org/10.1109/isvlsi.2003.1183355openalex-snapshot

A fine-grain Phased Logic CPU

inferred← citeshttps://doi.org/10.1109/iwrsp.2000.855207openalex-snapshot

The FLYSIG prototyping approach

inferred← citeshttps://doi.org/10.1109/lascas.2014.6820272openalex-snapshot

Using FPGAs to implement asynchronous pipelines

inferred← citeshttps://doi.org/10.1109/mwscas.1999.867316openalex-snapshot

Efficient implementation for high accuracy DCT processor based on FPGA

inferred← citeshttps://doi.org/10.1109/mwscas.2000.952852openalex-snapshot

Design and prototyping of a ΣΔ decimator filter for DECT standard

inferred← citeshttps://doi.org/10.1109/sbcci.2001.953019openalex-snapshot

A fast asynchronous re-configurable architecture for multimedia applications

inferred← citeshttps://doi.org/10.1109/tcad.2021.3131546openalex-snapshot

General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs

inferred← citeshttps://doi.org/10.1109/test.1997.639697openalex-snapshot

ACT: a DFT tool for self-timed circuits

inferred← citeshttps://doi.org/10.1155/2008/926851openalex-snapshot

Burst-Mode Asynchronous Controllers on FPGA

inferred← citeshttps://doi.org/10.1587/transele.e97.c.253openalex-snapshot

Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC

inferred← citeshttps://doi.org/10.1587/transinf.e93.d.2145openalex-snapshot

Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol

inferred← citeshttps://doi.org/10.5555/882483.883910openalex-snapshot

A Fast Asynchronous Re-Configurable Architecture for Multimedia Applications

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.