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Delay-insensitive codes — an overview
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01171114openalex-snapshot
Ein Satz �ber Untermengen einer endlichen Menge
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1016/s0019-9958(61)80037-5openalex-snapshot
A note on error detection codes for asymmetric channels
inferredcites →https://doi.org/10.1016/s0019-9958(62)90223-1openalex-snapshot
Optimal error detection codes for completely asymmetric binary channels
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Introduction to V.L.S.I. Systems
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Direct Implementation of Asynchronous Control Units
inferredcites →https://doi.org/10.1109/tc.1982.1676034openalex-snapshot
Theory of Unidirectional Error Correcting/Detecting Codes
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Heterogeneously encoded dual-bit self-timed adder
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BaBaNoC: An asynchronous network-on-chip described in Balsa
inferred← citeshttps://doi.org/10.1109/sbcci60457.2023.10261656openalex-snapshot
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V
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Transmission time analysis for the parallel asynchronous communication scheme
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Efficient encoding and decoding schemes for balanced codes
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Design and analysis of a self-timed duplex communication system
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Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels
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Conditional Partial Order Graphs: Model, Synthesis, and Application
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Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication
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Expandable Networks for Neuromorphic Chips
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NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization
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Reliable Communications Across Parallel Asynchronous Channels With Arbitrary Skews
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Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches
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Sparse Distributed Memory Using Rank-Order Neural Codes
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Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
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Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
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Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
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Design for Testability of Sleep Convention Logic
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Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip
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CMOS implementation of static threshold gates with hysteresis: A new approach
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Self-timed boundary-scan cells for multi-chip module test
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VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
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Single-rail handshake circuits
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High-level test evaluation of asynchronous circuits
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HIGH SPEED MULTI-RESOURCE ARBITER WITH ACTIVE VIRTUAL CHANNEL ALLOCATION FOR NETWORK ON CHIPS
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SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC
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Efficient synthesis of speed-independent combinational logic circuits
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Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
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From molecular interactions to gates
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Formal methods for the analysis and synthesis of nanometer-scale cellular arrays
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Asynchronous transient resilient links for NoC
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Resilient and adaptive performance logic
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