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A new explanation of the glitch phenomenon
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bf01660033openalex-snapshot
On the existence of delay-insensitive fair arbiters: Trace theory and its limitations
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1016/0141-9331(89)90152-xopenalex-snapshot
Parallel program design: a foundation
inferredcites →https://doi.org/10.1109/t-c.1973.223730openalex-snapshot
Anomalous Behavior of Synchronizer and Arbiter Circuits
inferredcites →https://doi.org/10.1109/tc.1981.6312173openalex-snapshot
General theory of metastable operation
inferredcites →https://doi.org/10.1145/3149.214121openalex-snapshot
Impossibility of distributed consensus with one faulty process
inferredcites →https://doi.org/10.13016/m2332copenalex-snapshot
Ambiguous Behavior of Logic Bistable Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s00446-002-0076-2openalex-snapshot
Arbitration-free synchronization
inferred← citeshttps://doi.org/10.1007/s11229-022-03843-3openalex-snapshot
Indecision and Buridan’s Principle
inferred← citeshttps://doi.org/10.1016/j.jtbi.2007.09.044openalex-snapshot
Systematic mistakes are likely in bounded optimal decision-making systems
inferred← citeshttps://doi.org/10.1016/s0304-3975(99)00273-xopenalex-snapshot
Delay-insensitivity and ternary simulation
inferred← citeshttps://doi.org/10.1051/ita/1994283-401591openalex-snapshot
Generalized ternary simulation of sequential circuits
inferred← citeshttps://doi.org/10.1080/0020174x.2024.2362938openalex-snapshot
Equal desires and self-control
inferred← citeshttps://doi.org/10.1109/ats.2012.40openalex-snapshot
Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment
inferred← citeshttps://doi.org/10.1117/12.884113openalex-snapshot
Rhythms essential to logical communication
inferred← citeshttps://doi.org/10.1145/3472410.3472420openalex-snapshot
Asynchronous Arbitration. Synthesis of Multi-input Asynchronous Arbiter with Consecutive Connection of Input Signals
inferred← citeshttps://doi.org/10.1145/72981.72982openalex-snapshot
A hundred impossibility proofs for distributed computing
inferred← citeshttps://doi.org/10.48550/arxiv.1106.1639openalex-snapshot
Rhythms of Memory and Bits on Edge: Symbol Recognition as a Physical Phenomenon
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