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Systolic implementation of digital filters

https://doi.org/10.1007/bf01941018

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-68402-9_28openalex-snapshot

A Two-Level Pipelined Systolic Array for Convolutions

inferredcites →https://doi.org/10.1007/978-3-642-87867-1_10openalex-snapshot

VLSI Array Architecture for Picture Processing

inferredcites →https://doi.org/10.1007/bf01816548openalex-snapshot

Realization of multidimensional digital transfer functions

inferredcites →https://doi.org/10.1016/0010-4485(86)90105-3openalex-snapshot

VLSI signal processing systems

inferredcites →https://doi.org/10.1016/0141-9331(86)90082-7openalex-snapshot

VLSI signal processing systems

inferredcites →https://doi.org/10.1049/ep.1980.0222openalex-snapshot

Digital Filters: Analysis and Design

inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot

Introduction to V.L.S.I. Systems

inferredcites →https://doi.org/10.1109/29.17537openalex-snapshot

A systolic realization for 2-D digital filters

inferredcites →https://doi.org/10.1109/31.1789openalex-snapshot

2-D filter implementations for real-time signal processing

inferredcites →https://doi.org/10.1109/31.55027openalex-snapshot

Realization of multidimensional GIC digital filters

inferredcites →https://doi.org/10.1109/5.4402openalex-snapshot

Regular iterative algorithms and their implementation on processor arrays

inferredcites →https://doi.org/10.1109/iscas.1990.112285openalex-snapshot

Systolic implementations of two-dimensional recursive digital filters

inferredcites →https://doi.org/10.1109/massp.1985.1163741openalex-snapshot

VLSI Array processors

inferredcites →https://doi.org/10.1109/mc.1982.1653825openalex-snapshot

Why systolic architectures?

inferredcites →https://doi.org/10.1109/proc.1985.13358openalex-snapshot

Multidimensional digital signal processing

inferredcites →https://doi.org/10.1109/tc.1983.1676177openalex-snapshot

VLSI Array Design Under Constraint of Limited I/O Bandwidth

inferredcites →https://doi.org/10.1109/visual.1996.567600openalex-snapshot

Temporal continuity of levels of detail in Delaunay triangulated terrain

inferredcites →https://doi.org/10.1184/r1/6603170openalex-snapshot

An algebra for VLSI algorithm design

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9780470932025.refsopenalex-snapshot

References

inferred← citeshttps://doi.org/10.1007/bf02106104openalex-snapshot

Mapping 3-D IIR digital filter onto systolic arrays

inferred← citeshttps://doi.org/10.1109/30.286404openalex-snapshot

Systolic and semi-systolic realizations of three dimensional filters

inferred← citeshttps://doi.org/10.1109/76.260196openalex-snapshot

Systolic implementation of multidimensional nonrecursive digital filters

inferred← citeshttps://doi.org/10.1109/78.492569openalex-snapshot

High-speed systolic ladder structures for multidimensional recursive digital filters

inferred← citeshttps://doi.org/10.1109/acssc.1994.471617openalex-snapshot

VLSI array processors for linear-phase FIR filters

inferred← citeshttps://doi.org/10.1109/acssc.1995.540850openalex-snapshot

Real-time 3-dimensional recursive digital filter for video signals

inferred← citeshttps://doi.org/10.1109/ccece.1993.332387openalex-snapshot

Systolic implementation of linear-phase FIR filters

inferred← citeshttps://doi.org/10.1109/ccece.1993.332390openalex-snapshot

Systolic implementation of fractional decimators and interpolators

inferred← citeshttps://doi.org/10.1109/icecs.2000.911608openalex-snapshot

A tool for two's complement, bit-level, fixed-point simulation of digital filters

inferred← citeshttps://doi.org/10.1109/iscas.1995.521619openalex-snapshot

VLSI implementation of a new bit-level pipelined architecture for 2-D allpass digital filters

inferred← citeshttps://doi.org/10.1109/iscas.1996.541821openalex-snapshot

A real-time video implementation of a three-dimensional first-order recursive discrete-time filter

inferred← citeshttps://doi.org/10.1109/mwscas.1993.343223openalex-snapshot

Systolic implementation of FIR decimators and interpolators

inferred← citeshttps://doi.org/10.1109/mwscas.1994.518924openalex-snapshot

Systolic implementation of polyphase decimators and interpolators

inferred← citeshttps://doi.org/10.1109/pacrim.1993.407152openalex-snapshot

QMF banks design and implementation perspectives

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