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Mapping 3-D IIR digital filter onto systolic arrays

https://doi.org/10.1007/bf02106104
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/9781118627372openalex-snapshot
Integer and Combinatorial Optimization
inferredcites →https://doi.org/10.1007/978-1-4612-1098-6openalex-snapshot
Computational Geometry
inferredcites →https://doi.org/10.1007/978-3-642-04898-2_552openalex-snapshot
Statistical Signal Processing
inferredcites →https://doi.org/10.1007/978-3-642-68402-9_27openalex-snapshot
Digital Signal Processing Applications of Systolic Algorithms
inferredcites →https://doi.org/10.1007/bf01558666openalex-snapshot
Synthesizing systolic arrays with control signals from recurrence equations
inferredcites →https://doi.org/10.1007/bf01941018openalex-snapshot
Systolic implementation of digital filters
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1007/bf02477176openalex-snapshot
The mapping of linear recurrence equations on regular arrays
inferredcites →https://doi.org/10.1007/bf02477177openalex-snapshot
Scheduling a system of nonsingular affine recurrence equations onto a processor array
inferredcites →https://doi.org/10.1057/jors.1987.94openalex-snapshot
Theory of Linear and Integer Programming
inferredcites →https://doi.org/10.1109/29.17537openalex-snapshot
A systolic realization for 2-D digital filters
inferredcites →https://doi.org/10.1109/78.80972openalex-snapshot
An improved systolic architecture for 2-D digital filters
inferredcites →https://doi.org/10.1109/mc.1982.1653825openalex-snapshot
Why systolic architectures?
inferredcites →https://doi.org/10.1109/mc.1985.1662798openalex-snapshot
A Transformational Model of VLSI Systolic Design
inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot
On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/proc.1987.13882openalex-snapshot
Array architectures for iterative algorithms
inferredcites →https://doi.org/10.1109/sfcs.1981.34openalex-snapshot
Optimizing synchronous systems
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/378456.378484openalex-snapshot
Volume rendering
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1145/800015.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1201/9781315219141-28openalex-snapshot
VLSI Implementation of Digital FIlters
inferredcites →https://doi.org/10.2307/2153000openalex-snapshot
Fundamentals of Matrix Computations.
inferredcites →https://doi.org/10.2307/253980openalex-snapshot
Theory of Linear and Integer Programming
inferredcites →https://doi.org/10.56021/9781421407944openalex-snapshot
Matrix Computations

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9780470932025.refsopenalex-snapshot
References
inferred← citeshttps://doi.org/10.1007/s11045-006-0003-yopenalex-snapshot
A hierarchical design methodology for full-search block matching motion estimation
inferred← citeshttps://doi.org/10.1007/s13369-014-1363-5openalex-snapshot
Low-Power, High-Speed Unified and Scalable Word-Based Radix 8 Architecture for Montgomery Modular Multiplication in GF(P) and GF(2 n )
inferred← citeshttps://doi.org/10.1109/82.868458openalex-snapshot
A fast parallel multiplier-accumulator using the modified Booth algorithm
inferred← citeshttps://doi.org/10.1109/bwcca.2011.51openalex-snapshot
Finite Field Multiplication Using Reordered Normal Basis Multiplier
inferred← citeshttps://doi.org/10.1109/cjece.2009.5599422openalex-snapshot
High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm
inferred← citeshttps://doi.org/10.1109/iacs.2019.8809140openalex-snapshot
Scalable and Parameterizable Processor Array Architecture for Similarity Distance Computation
inferred← citeshttps://doi.org/10.1109/ic_aset65966.2025.11232175openalex-snapshot
A Systematic Methodology to Design a Scalable Hardware Accelerator for 2D Convolution
inferred← citeshttps://doi.org/10.1109/iceec.2004.1374443openalex-snapshot
A systolic array structure for string searching
inferred← citeshttps://doi.org/10.1109/icm.2007.4497662openalex-snapshot
A high-speed, low-area processor array architecture for multiplication over GF(2m)
inferred← citeshttps://doi.org/10.1109/idt.2007.4437465openalex-snapshot
A High-Speed, Low-Area Processor Array Architecture for Multiplication and Squaring over GF(2m)
inferred← citeshttps://doi.org/10.1109/isspit.2004.1433692openalex-snapshot
Hierarchical systolic array design for full-search block matching motion estimation
inferred← citeshttps://doi.org/10.1109/isspit.2004.1433693openalex-snapshot
Processor array design for deep packet classification
inferred← citeshttps://doi.org/10.1109/itict.2007.4475666openalex-snapshot
A low-area, high-speed, processor array architecture for field ALU over GF (2m)
inferred← citeshttps://doi.org/10.1109/iwsoc.2005.104openalex-snapshot
Systolic array-based string matching unit for spam blocking
inferred← citeshttps://doi.org/10.1109/jeeit.2019.8717517openalex-snapshot
Linear Processor Array Architectures for Similarity Distance Computation
inferred← citeshttps://doi.org/10.1109/tpds.2006.39openalex-snapshot
Processor array architectures for deep packet classification
inferred← citeshttps://doi.org/10.1109/tpds.2010.196openalex-snapshot
Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm
inferred← citeshttps://doi.org/10.1109/tpds.2017.2656900openalex-snapshot
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2358196openalex-snapshot
Systolic Array Architectures for Sunar–Koç Optimal Normal Basis Type II Multiplier
inferred← citeshttps://doi.org/10.1155/2019/3185137openalex-snapshot
Low-Complexity Scalable Architectures for Parallel Computation of Similarity Measures
inferred← citeshttps://doi.org/10.1587/transfun.e99.a.683openalex-snapshot
Novel Reconfigurable Hardware Accelerator for Protein Sequence Alignment Using Smith-Waterman Algorithm
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