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A shift register architecture for high-speed data sorting

https://doi.org/10.1007/bf02107058
0 signed · 22 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/0167-9260(93)90060-popenalex-snapshot
VLSI implementation of an M-array image filter based on shift register array
inferredcites →https://doi.org/10.1109/29.103069openalex-snapshot
Application-specific architectural methodologies for high-throughput digital signal and image processing
inferredcites →https://doi.org/10.1109/30.234627openalex-snapshot
An area-efficient median filtering IC for image/video applications
inferredcites →https://doi.org/10.1109/tassp.1980.1163426openalex-snapshot
A fast method for real-time median filtering
inferredcites →https://doi.org/10.1109/tassp.1986.1164980openalex-snapshot
A new algorithm for real-time median filtering
inferredcites →https://doi.org/10.1201/9781315364094-7openalex-snapshot
Signal and image processing

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.mejo.2009.08.006openalex-snapshot
A versatile linear insertion sorter based on an FIFO scheme
inferred← citeshttps://doi.org/10.1016/j.prime.2024.100540openalex-snapshot
A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors
inferred← citeshttps://doi.org/10.1109/71.744832openalex-snapshot
Data-driven control scheme for linear arrays: application to a stable insertion sorter
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00021openalex-snapshot
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470730openalex-snapshot
A configurable high-throughput linear sorter system
inferred← citeshttps://doi.org/10.1109/isvlsi.2008.14openalex-snapshot
A Versatile Linear Insertion Sorter Based on a FIFO Scheme
inferred← citeshttps://doi.org/10.1109/miel52794.2021.9569153openalex-snapshot
A Chisel Generator of Parameterizable and Runtime Reconfigurable Linear Insertion Streaming Sorters
inferred← citeshttps://doi.org/10.1109/tc.2022.3146509openalex-snapshot
FLiMS: a Fast Lightweight 2-way Merger for Sorting
inferred← citeshttps://doi.org/10.1109/tcad.2020.2977074openalex-snapshot
An Extended Nonstrict Partially Ordered Set-Based Configurable Linear Sorter on FPGAs
inferred← citeshttps://doi.org/10.1109/tcad.2024.3471903openalex-snapshot
MCSSA: A Stream-Based Multiconcurrency Systolic Sorting Array Combining Merge Tree
inferred← citeshttps://doi.org/10.1109/tcsi.2011.2177001openalex-snapshot
A Network-Efficient Nonbinary QC-LDPC Decoder Architecture
inferred← citeshttps://doi.org/10.1109/tcsii.2024.3377255openalex-snapshot
DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting
inferred← citeshttps://doi.org/10.1109/tpds.2024.3434332openalex-snapshot
SSA: A Uniformly Recursive Bidirection-Sequence Systolic Sorter Array
inferred← citeshttps://doi.org/10.1145/2854150openalex-snapshot
Streaming Sorting Networks
inferred← citeshttps://doi.org/10.1145/3430699openalex-snapshot
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
inferred← citeshttps://doi.org/10.1155/2011/963539openalex-snapshot
A Streaming High-Throughput Linear Sorter System with Contention Buffering
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