On the public citation graph
Streaming Sorting Networks
0 signed · 72 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_66openalex-snapshot
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
inferredcites →https://doi.org/10.1007/978-3-642-03034-5_18openalex-snapshot
Operator Language: A Program Generation Framework for Fast Kernels
inferredcites →https://doi.org/10.1007/bf01189337openalex-snapshot
A methodology for designing, modifying, and implementing Fourier transform algorithms on various architectures
inferredcites →https://doi.org/10.1007/bf02107058openalex-snapshot
A shift register architecture for high-speed data sorting
inferredcites →https://doi.org/10.1016/j.mejo.2009.08.006openalex-snapshot
A versatile linear insertion sorter based on an FIFO scheme
inferredcites →https://doi.org/10.1109/12.16500openalex-snapshot
Parallel sorting in two-dimensional VLSI models of computation
inferredcites →https://doi.org/10.1109/12.286307openalex-snapshot
Constant time sorting on reconfigurable meshes
inferredcites →https://doi.org/10.1109/ipdpsw.2010.5470730openalex-snapshot
A configurable high-throughput linear sorter system
inferredcites →https://doi.org/10.1109/ipps.1992.223059openalex-snapshot
An optimal sorting algorithm on reconfigurable mesh
inferredcites →https://doi.org/10.1109/iscas.2002.1010428openalex-snapshot
Design of a pipelined and expandable sorting architecture with simple control scheme
inferredcites →https://doi.org/10.1109/iscas.2007.378475openalex-snapshot
Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA
inferredcites →https://doi.org/10.1109/jproc.2004.840306openalex-snapshot
SPIRAL: Code Generation for DSP Transforms
inferredcites →https://doi.org/10.1109/t-c.1971.223205openalex-snapshot
Parallel Processing with the Perfect Shuffle
inferredcites →https://doi.org/10.1109/tc.1984.5009338openalex-snapshot
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
inferredcites →https://doi.org/10.1137/1.9781611970999openalex-snapshot
Computational Frameworks for the Fast Fourier Transform
inferredcites →https://doi.org/10.1145/1468075.1468121openalex-snapshot
Sorting networks and their applications
inferredcites →https://doi.org/10.1145/1502793.1502799openalex-snapshot
Permuting streaming data using RAMs
inferredcites →https://doi.org/10.1145/2159542.2159547openalex-snapshot
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
inferredcites →https://doi.org/10.1145/2228360.2228588openalex-snapshot
Computer generation of streaming sorting networks
inferredcites →https://doi.org/10.1145/2684746.2689068openalex-snapshot
Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA
inferredcites →https://doi.org/10.1145/321450.321457openalex-snapshot
An Adaptation of the Fast Fourier Transform for Parallel Processing
inferredcites →https://doi.org/10.1145/76359.76362openalex-snapshot
The periodic balanced sorting network
inferredcites →https://doi.org/10.1155/2000/14617openalex-snapshot
An Efficient Parallel VLSI Sorting Architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/access.2020.3047594openalex-snapshot
Design, Implementation, and Analysis of High-Speed Single-Stage N-Sorters and N-Filters
inferred← citeshttps://doi.org/10.1109/access.2026.3669391openalex-snapshot
Fast and Efficient Merge of Sorted Input Lists in Hardware Using List Offset Merge Sorters
inferred← citeshttps://doi.org/10.1109/arith.2017.13openalex-snapshot
Optimal Streamed Linear Permutations
inferred← citeshttps://doi.org/10.1109/arith.2019.00043openalex-snapshot
DSL-Based Modular IP Core Generators: Example FFT and Related Structures
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473968openalex-snapshot
PRIMATE: Processing in Memory Acceleration for Dynamic Token-pruning Transformers
inferred← citeshttps://doi.org/10.1109/ei264398.2024.10990559openalex-snapshot
FPGA-based Voltage Balancing Control for MMC
inferred← citeshttps://doi.org/10.1109/fccm.2019.00067openalex-snapshot
Sorting Large Data Sets with FPGA-Accelerated Samplesort
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00021openalex-snapshot
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics
inferred← citeshttps://doi.org/10.1109/gcat55367.2022.9972111openalex-snapshot
An Efficient Quasi Comparison-free Bidirectional Architecture for Sorting Algorithm
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10070989openalex-snapshot
Duet: Creating Harmony between Processors and Embedded FPGAs
inferred← citeshttps://doi.org/10.1109/icecs53924.2021.9665482openalex-snapshot
A Design Generator of Parametrizable and Runtime Configurable Constant False Alarm Rate Processors
inferred← citeshttps://doi.org/10.1109/ieeeconf60004.2024.10942935openalex-snapshot
Stable Single-Stage 2-Way Merge Sorters
inferred← citeshttps://doi.org/10.1109/ises52644.2021.00015openalex-snapshot
Low Power Sorters Using Clock Gating
inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00028openalex-snapshot
Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads
inferred← citeshttps://doi.org/10.1109/isvlsi65124.2025.11130285openalex-snapshot
Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA
inferred← citeshttps://doi.org/10.1109/miel52794.2021.9569153openalex-snapshot
A Chisel Generator of Parameterizable and Runtime Reconfigurable Linear Insertion Streaming Sorters
inferred← citeshttps://doi.org/10.1109/nss/mic44845.2022.10399214openalex-snapshot
Compact Design of an FPGA Based Data Acquisition (DAQ) System for an RF-penetrable TOF-PET Brain Dedicated Insert
inferred← citeshttps://doi.org/10.1109/tc.2017.2672966openalex-snapshot
Hardware Design of Low-Power High-Throughput Sorting Unit
inferred← citeshttps://doi.org/10.1109/tc.2022.3169434openalex-snapshot
Sky-Sorter: A Processing-in-Memory Architecture for Large-Scale Sorting
inferred← citeshttps://doi.org/10.1109/tc.2026.3653702openalex-snapshot
FractalSort: High Precision Compressed Radix Sort on FPGA
inferred← citeshttps://doi.org/10.1109/tcsi.2020.2969325openalex-snapshot
Polar Compiler: Auto-Generator of Hardware Architectures for Polar Encoders
inferred← citeshttps://doi.org/10.1109/tcsi.2020.3048955openalex-snapshot
A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm
inferred← citeshttps://doi.org/10.1109/tcsi.2023.3342929openalex-snapshot
A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm
inferred← citeshttps://doi.org/10.1109/tcsii.2024.3377255openalex-snapshot
DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting
inferred← citeshttps://doi.org/10.1109/tevc.2019.2918212openalex-snapshot
Evolutionary Development of Growing Generic Sorting Networks by Means of Rewriting Systems
inferred← citeshttps://doi.org/10.1109/tim.2023.3328091openalex-snapshot
Compact FPGA-Based Data Acquisition System for a High-Channel, High-Count-Rate TOF-PET Insert for Brain PET/MRI
inferred← citeshttps://doi.org/10.1109/tpds.2017.2705128openalex-snapshot
Computer Generation of High Throughput and Memory Efficient Sorting Designs on FPGA
inferred← citeshttps://doi.org/10.1109/tpds.2018.2874002openalex-snapshot
Massively Parallel Tree Search for High-Dimensional Sphere Decoders
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2661746openalex-snapshot
An Efficient O( $N$ ) Comparison-Free Sorting Algorithm
inferred← citeshttps://doi.org/10.1109/tvlsi.2020.2983975openalex-snapshot
Autogeneration of Pipelined Belief Propagation Polar Decoders
inferred← citeshttps://doi.org/10.1145/2847263.2847277openalex-snapshot
Optimal Circuits for Streamed Linear Permutations Using RAM
inferred← citeshttps://doi.org/10.1145/3174243.3174269openalex-snapshot
A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs
inferred← citeshttps://doi.org/10.1145/3359754openalex-snapshot
DSL-Based Hardware Generation with Scala
inferred← citeshttps://doi.org/10.1145/3373087.3375304openalex-snapshot
FPGA-Accelerated Samplesort for Large Data Sets
inferred← citeshttps://doi.org/10.1145/3579371.3589052openalex-snapshot
Supply Chain Aware Computer Architecture
inferred← citeshttps://doi.org/10.1145/3688612openalex-snapshot
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product
inferred← citeshttps://doi.org/10.1145/3734797openalex-snapshot
Sorting it out in Hardware: A State-of-the-Art Survey
inferred← citeshttps://doi.org/10.1145/3748173.3779193openalex-snapshot
EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter
inferred← citeshttps://doi.org/10.14569/ijacsa.2019.0101203openalex-snapshot
Best-Choice Topology: An Optimized Array-based Maximum Finder
inferred← citeshttps://doi.org/10.23919/mixdes58562.2023.10203246openalex-snapshot
A Hardware Design Generator of High-Performance FIFO-Based Linear Insertion Streaming Sorters
inferred← citeshttps://doi.org/10.46586/tches.v2018.i3.69-88openalex-snapshot
Data Flow Oriented Hardware Design of RNS-based Polynomial Multiplication for SHE Acceleration
inferred← citeshttps://doi.org/10.48550/arxiv.2501.14815openalex-snapshot
A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs
inferred← citeshttps://doi.org/10.5755/j01.eie.23.3.18336openalex-snapshot
Fast Processing of Non-Repeated Values in Hardware
inferred← citeshttps://doi.org/10.70675/1338337bz06cdz4479z817dzff2ea8b914e9openalex-snapshot
Hardware Acceleration for Homomorphic Encryption
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.