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Performance of iterative computation in self-timed rings

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1016/s0022-0000(71)80013-2openalex-snapshot
Marked directed graphs
inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot
Introduction to V.L.S.I. Systems
inferredcites →https://doi.org/10.1109/4.98986openalex-snapshot
A zero-overhead self-timed 160-ns 54-b CMOS divider
inferredcites →https://doi.org/10.1109/43.41504openalex-snapshot
Automatic synthesis of asynchronous circuits from high-level specifications
inferredcites →https://doi.org/10.1109/tse.1980.230492openalex-snapshot
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
inferredcites →https://doi.org/10.1145/63526.63532openalex-snapshot
Micropipelines
inferredcites →https://doi.org/10.21236/ada447732openalex-snapshot
Performance Analysis and Optimization of Asynchronous Circuits Produced by Martin Synthesis
inferredcites →https://doi.org/10.21236/ada447734openalex-snapshot
Performance Analysis and Optimization of Asynchronous Circuits
inferredcites →https://doi.org/10.6100/ir25052openalex-snapshot
Classification and composition of delay-insensitive circuits
inferredcites →https://doi.org/10.7146/dpb.v16i228.7577openalex-snapshot
Self-Timed Iteration

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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References
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Prevent Deadlock and Remove Blocking for Self-Timed Systems
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Elasticity and Petri Nets
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Self timed division and square-root extraction
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Elastic systems
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Optimal asynchronous linear-pipelines
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Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
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Delay analysis of micropipelines
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Microarchitectural Transformations Using Elasticity
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Low-Power Asynchronous Processors
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Static timing analysis for self resetting circuits
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Asynchronous SRT dividers: the real cost
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Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography
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