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Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4419-6865-4openalex-snapshot
On-Chip Interconnect with aelite: Composable and Predictable Systems
inferredcites →https://doi.org/10.1007/978-1-4757-3385-3openalex-snapshot
Principles of Asynchronous Circuit Design
inferredcites →https://doi.org/10.1007/bf02108187openalex-snapshot
Performance of iterative computation in self-timed rings
inferredcites →https://doi.org/10.1109/12.475126openalex-snapshot
An algorithm for exact bounds on the time separation of events in concurrent systems
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/5.469298openalex-snapshot
Service disciplines for guaranteed performance service in packet-switching networks
inferredcites →https://doi.org/10.1109/acsd.2012.27openalex-snapshot
Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip
inferredcites →https://doi.org/10.1109/async.2005.7openalex-snapshot
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
inferredcites →https://doi.org/10.1109/date.2007.364399openalex-snapshot
Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO
inferredcites →https://doi.org/10.1109/date.2012.6176639openalex-snapshot
P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator
inferredcites →https://doi.org/10.1109/dsd.2013.40openalex-snapshot
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip
inferredcites →https://doi.org/10.1109/iccd.1993.393387openalex-snapshot
An algorithm for exact bounds on the time separation of events in concurrent systems
inferredcites →https://doi.org/10.1109/nanonet.2006.346219openalex-snapshot
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach
inferredcites →https://doi.org/10.1109/nocs.2007.14openalex-snapshot
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures
inferredcites →https://doi.org/10.1109/nocs.2012.25openalex-snapshot
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems
inferredcites →https://doi.org/10.1109/tvlsi.2007.898732openalex-snapshot
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines
inferredcites →https://doi.org/10.1145/1403375.1403717openalex-snapshot
Developing mesochronous synchronizers to enable 3D NoCs
inferredcites →https://doi.org/10.1145/1837274.1837353openalex-snapshot
The aethereal network on chip after ten years
inferredcites →https://doi.org/10.1145/1930037.1930045openalex-snapshot
Mesochronous NoC technology for power-efficient GALS MPSoCs
inferredcites →https://doi.org/10.5555/1266366.1266551openalex-snapshot
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
inferredcites →https://doi.org/10.5555/2485288.2485538openalex-snapshot
An area-efficient network interface for a TDM-based network-on-chip
inferredcites →https://doi.org/10.7873/date.2013.079openalex-snapshot
A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems
inferredcites →https://doi.org/10.7873/date.2013.217openalex-snapshot
An Area-efficient Network Interface for a TDM-based Network-on-Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-16214-0_16openalex-snapshot
Survey on Real-Time Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1007/978-981-13-8942-9_37openalex-snapshot
Design and Implementation of Argo NI-NoC Micro-architecture for MPSoC Using GALS Architecture
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.04.002openalex-snapshot
T-CREST: Time-predictable multi-core architecture for embedded systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2017.02.001openalex-snapshot
A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip
inferred← citeshttps://doi.org/10.1109/async.2019.00013openalex-snapshot
A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols
inferred← citeshttps://doi.org/10.1109/ecctd.2015.7300101openalex-snapshot
The Argo NOC: Combining TDM and GALS
inferred← citeshttps://doi.org/10.1109/ieeedata.2026.3667650openalex-snapshot
Descriptor: Asynchronous Circuit Logic Dataset (ACLD)
inferred← citeshttps://doi.org/10.1109/isorcw.2015.57openalex-snapshot
Models of Communication for Multicore Processors
inferred← citeshttps://doi.org/10.1109/ngcas.2017.73openalex-snapshot
Timing Organization of a Real-Time Multicore Processor
inferred← citeshttps://doi.org/10.1109/nocs.2014.7008774openalex-snapshot
A loosely synchronizing asynchronous router for TDM-scheduled NOCs
inferred← citeshttps://doi.org/10.1109/norchip.2014.7004739openalex-snapshot
Open core protocol (OCP) clock domain crossing interfaces
inferred← citeshttps://doi.org/10.1109/norchip.2014.7004742openalex-snapshot
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools
inferred← citeshttps://doi.org/10.1109/pdp.2016.36openalex-snapshot
Avionics Applications on a Time-Predictable Chip-Multiprocessor
inferred← citeshttps://doi.org/10.1109/rtas.2016.7461363openalex-snapshot
Temporal Isolation of Hard Real-Time Applications on Many-Core Processors
inferred← citeshttps://doi.org/10.1109/tetc.2017.2765825openalex-snapshot
High Performance Dynamic Resource Allocation for Guaranteed Service in Network-on-Chips
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2405614openalex-snapshot
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
inferred← citeshttps://doi.org/10.1145/2834848.2834851openalex-snapshot
Flexible TDM-based resource management in on-chip networks
inferred← citeshttps://doi.org/10.1145/2994133.2994141openalex-snapshot
Reconfigurable Links for Self-Timed On-Chip Communication
inferred← citeshttps://doi.org/10.1145/3015037.3015047openalex-snapshot
Support for the logical execution time model on a time-predictable multicore processor
inferred← citeshttps://doi.org/10.26053/0h-ganc-r8g0openalex-snapshot
Design and integration of high speed relative timed network-on-chip routers
inferred← citeshttps://doi.org/10.4230/oasics.wcet.2014.53openalex-snapshot
A Time-Predictable Memory Network-on-Chip
inferred← citeshttps://doi.org/10.5555/2755753.2757066openalex-snapshot
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation
inferred← citeshttps://doi.org/10.70675/714cfccfz5715z4059zacfbzdf7c8d93a2d1openalex-snapshot
Minimising shared resource contention when scheduling real-time applications on multi-core architectures
inferred← citeshttps://doi.org/10.70675/977a83d4z9a75z4155z9917zfb2237dfcb7copenalex-snapshot
Predictable execution on many-core processors
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