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A formal approach to designing delay-insensitive circuits

https://doi.org/10.1007/bf02252954
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Trace theory and systolic computations
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The translation of processes into circuits
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Networks of communicating processes and their (De-)composition
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Concurrent Computations and VLSI Circuits
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A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
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Trace Theory and VLSJ Design
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Communicating sequential processes
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Switching and Finite Automata Theory
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Introduction to V.L.S.I. Systems
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VLSI programming and silicon compilation-a novel approach from Philips research
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Minimum propagation delays in VLSI
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Anomalous Behavior of Synchronizer and Arbiter Circuits
inferredcites →https://doi.org/10.1109/tsmc.1973.4309232openalex-snapshot
Asynchronous Sequential Switching Circuits
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Macromodular computer systems
inferredcites →https://doi.org/10.1145/357980.358021openalex-snapshot
Communicating sequential processes
inferredcites →https://doi.org/10.1145/359576.359585openalex-snapshot
Communicating sequential processes
inferredcites →https://doi.org/10.1145/63526.63532openalex-snapshot
Micropipelines
inferredcites →https://doi.org/10.6100/ir25052openalex-snapshot
Classification and composition of delay-insensitive circuits
inferredcites →https://doi.org/10.6100/ir272918openalex-snapshot
Translating programs into delay-insensitive circuits
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
inferredcites →https://doi.org/10.7907/zmy86-a1w29openalex-snapshot
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits

What points at this work

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