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DSP design tool requirements for embedded systems: A telecommunications industrial perspective

https://doi.org/10.1007/bf02406469
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Global Scheduling and Allocation Algorithms in the HAL System
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Microcontrol architectures with sequencing firmware and modular microcode development tools
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STATEMATE: a working environment for the development of complex reactive systems
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An integrated CAD system for algorithm-specific IC design
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The high-level synthesis of digital systems
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Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms
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Algorithms for high-level synthesis
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Visual register-transfer description of VLSI microarchitectures
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High level synthesis of pipelined instruction set processors and back-end compilers
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The Sprite Input Language-an intermediate format for high level synthesis
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HYPER: an interactive synthesis environment for high performance real time applications
inferredcites →https://doi.org/10.1109/iscas.1992.230671openalex-snapshot
Design automation technology for codesign: status and directions
inferredcites →https://doi.org/10.1109/micro.1988.639247openalex-snapshot
Flexible Processors: A Promising Application-specific Processor Design Approach
inferredcites →https://doi.org/10.1109/micro.1988.639268openalex-snapshot
Lazy Data Routing And Greedy Scheduling For Application-specific Signal Processors
inferredcites →https://doi.org/10.1109/ms.1986.234070openalex-snapshot
Microcode Optimization: Examples and Approaches
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Architecture synthesis of high-performance application-specific processors
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A visual microprogramming system
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Optimal Code Generation for Expression Trees
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An interactive tool for register-level structure optimization
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Cost-effective design of application specific VLIW processors using the SCARCE framework
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MIES: a microarchitecture design tool
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ASIC microprocessors
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High level synthesis of pipelined instruction set processors and back-end compilers
inferredcites →https://doi.org/10.5555/62504.62512openalex-snapshot
Flexible processors: a promising application-specific processor design approach
inferredcites →https://doi.org/10.5555/62504.62676openalex-snapshot
Lazy data routing and greedy scheduling for application-specific signal processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Instruction Selection
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Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
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Hardware/Software Co-Design: Application Domains and Design Technologies
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Trends In Embedded Systems Technology
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Co-Design of DSP Systems
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Programmable Chips In Consumer Electronics and Telecommunications
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Effective Heterogenous Design and Co-Simulation
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Multilanguage Specification for System Design
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Embedded system design
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Custom DSP design of a GSM speech coder
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Synthesis for real time systems: Solutions and challenges
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Scheduling with register constraints for DSP architectures
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Design of Embedded Systems: Formal Models, Validation, and Synthesis
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Constraint Analysis for DSP Code Generation Manuscript received April 1, 1998; revised August 27, 1998. This paper was recommended by Associate Editor G. Borriello. Publisher Item Identifier S 0278-0070(99)00810-6.
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Subsetting Behavioral Intellectual Property for Low Power ASIP Design
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VLIW Processor Codesign for Video Processing
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ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration
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Reconfigurable Filter Coprocessor Architecture for DSP Applications
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Hardware/software partitioning for multifunction systems
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Constraint analysis for DSP code generation
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Hardware-software co-design of embedded systems
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Hardware/software co-design
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Design of embedded systems: formal models, validation, and synthesis
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Hardware/software co-design of digital telecommunication systems
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Embedded software in real-time signal processing systems: application and architecture trends
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MetaCore: an application-specific programmable DSP development system
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Processor-core based design and test
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A Transformation-Based Approach for Storage Optimization
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Code Generation For Core Processors
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ISDL: An Instruction Set Description Language For Retargetability
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A constraint driven approach to loop pipelining and register binding
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Embedded software: how to make it efficient?
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Instruction-set matching and selection for DSP and ASIP code generation
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High-level synthesis and codesign methods: An application to a Videophone Codec
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A neuro-fuzzy real-time image processing system
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A prototyping method of embedded real time systems for signal processing applications
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A new approach to DSP intrinsic functions
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Flexible modeling environment for embedded systems design
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Generating Instruction Sets And Microarchitectures From Applications
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Design Of Heterogeneous Ics For Mobile And Personal Communication Systems
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Improving design turnaround time via two-levels HW/SW co-simulation
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Parallel Algorithms for FIR Computation Mapped to ESCA Architecture
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Instruction-set matching and GA-based selection for embedded-processor code generation
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Data routing: a paradigm for efficient data-path synthesis and code generation
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Industrial experience using rule-driven retargetable code generation for multimedia applications
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WWW based structuring of codesigns
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Register files constraint satisfaction during scheduling of DSP code
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Pipelined array-based FIR filter folding
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Optimistic coalescing for heterogeneous register architectures
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Optimistic coalescing for heterogeneous register architectures
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Register coalescing techniques for heterogeneous register architecture with copy sifting
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Manifestations of heterogeneity in hardware/software co-design
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WWW based structuring of codesigns
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Code generation for core processors
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ISDL
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Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining
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Application-specific memory management for embedded systems using software-controlled caches
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Constraint analysis for code generation
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Partitioning of embedded applications onto heterogeneous multiprocessor architectures
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Hardware/Software Cosynthesis of DSP Systems
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Address optimizations for embedded processors
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Memory optimization techniques for embedded systems
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Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach
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Generating instruction sets and microarchitectures from applications
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Register assignrnent through resource classification for ASIP microcode generation
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Design of heterogeneous ICs for mobile and personal communication systems
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High-level synthesis and codesign methods: an application to a videophone codec
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Data routing: a paradigm for efficient data-path synthesis and code generation
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An integrated approach to retargetable code generation
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Transformational partitioning for co-design of multiprocessor systems
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Hardware/software partitioning for multi-function systems
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