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Embedded system design

https://doi.org/10.1007/bf00134682
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/j.1538-7305.1993.tb00516.xopenalex-snapshot
The Video Communications Decade
inferredcites →https://doi.org/10.1002/j.1538-7305.1993.tb00523.xopenalex-snapshot
Image and Video Coding Standards
inferredcites →https://doi.org/10.1002/spe.4380140406openalex-snapshot
Attributed linear intermediate representations for retargetable code generators
inferredcites →https://doi.org/10.1007/3-540-57877-3_29openalex-snapshot
Transport-triggering vs. operation-triggering
inferredcites →https://doi.org/10.1007/978-0-387-34920-6_37openalex-snapshot
Cosynthesis In CASTLE
inferredcites →https://doi.org/10.1007/978-1-4613-1519-3openalex-snapshot
Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench
inferredcites →https://doi.org/10.1007/978-1-4615-2307-9_10openalex-snapshot
Portable Video-on-Demand in Wireless Communication
inferredcites →https://doi.org/10.1007/978-1-4615-2323-9_10openalex-snapshot
Local Microcode Generation in System Design
inferredcites →https://doi.org/10.1007/978-1-4615-2323-9_14openalex-snapshot
Code Generation for Transport Triggered Architectures
inferredcites →https://doi.org/10.1007/978-1-4615-3506-5_3openalex-snapshot
VLSI Architectures for Digital Video Signal Processing
inferredcites →https://doi.org/10.1007/978-1-4615-3626-0openalex-snapshot
Vector Quantization and Signal Compression
inferredcites →https://doi.org/10.1007/978-1-4615-3626-0_16openalex-snapshot
Adaptive Vector Quantization
inferredcites →https://doi.org/10.1007/978-1-4615-3636-9openalex-snapshot
High — Level Synthesis
inferredcites →https://doi.org/10.1007/978-1-4615-3966-7openalex-snapshot
High-Level VLSI Synthesis
inferredcites →https://doi.org/10.1007/978-1-4615-3966-7_10openalex-snapshot
Architectural Optimization Methods for Control-Dominated Machines
inferredcites →https://doi.org/10.1007/978-1-4615-3966-7_2openalex-snapshot
Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment
inferredcites →https://doi.org/10.1007/978-1-4615-3966-7_4openalex-snapshot
The IBM High-Level Synthesis System
inferredcites →https://doi.org/10.1007/978-1-4615-3966-7_5openalex-snapshot
MICON: Automated Design of Computer Systems
inferredcites →https://doi.org/10.1007/978-1-4615-3966-7_9openalex-snapshot
Synthesis From Pure Behavioral Descriptions
inferredcites →https://doi.org/10.1007/978-1-4615-3968-1openalex-snapshot
A Survey of High-Level Synthesis Systems
inferredcites →https://doi.org/10.1007/978-1-4757-2222-2openalex-snapshot
High-Level Synthesis for Real-Time Digital Signal Processing
inferredcites →https://doi.org/10.1007/978-1-4757-2231-4openalex-snapshot
Synchronous Programming of Reactive Systems
inferredcites →https://doi.org/10.1007/978-3-662-09507-2_22openalex-snapshot
The C Programming Language
inferredcites →https://doi.org/10.1007/978-94-009-0187-2_14openalex-snapshot
Emulation and Prototyping Of Digital Systems
inferredcites →https://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferredcites →https://doi.org/10.1007/bf01215398openalex-snapshot
A comparison of fast inverse discrete cosine transform algorithms
inferredcites →https://doi.org/10.1007/bf02406469openalex-snapshot
DSP design tool requirements for embedded systems: A telecommunications industrial perspective
inferredcites →https://doi.org/10.1007/bfb0024530openalex-snapshot
Event-triggered versus time-triggered real-time systems
inferredcites →https://doi.org/10.1007/bfb0028726openalex-snapshot
Synchronous programming of reactive systems
inferredcites →https://doi.org/10.1016/0096-0551(81)90048-5openalex-snapshot
Register allocation via coloring
inferredcites →https://doi.org/10.1016/0923-5965(92)90019-copenalex-snapshot
The MPEG video compression algorithm
inferredcites →https://doi.org/10.1016/b978-0-08-091854-9.50016-6openalex-snapshot
Image and Video Coding Standards
inferredcites →https://doi.org/10.1016/b978-0-08-092534-9.50007-2openalex-snapshot
DISCRETE COSINE TRANSFORM
inferredcites →https://doi.org/10.1063/1.4823127openalex-snapshot
Ten Lectures on Wavelets
inferredcites →https://doi.org/10.1105/tpc.2.12.1171openalex-snapshot
Identification of an enhancer element for the endosperm-specific expression of high molecular weight glutenin.
inferredcites →https://doi.org/10.1109/12.204789openalex-snapshot
A characterization of binary decision diagrams
inferredcites →https://doi.org/10.1109/2.108047openalex-snapshot
Biting the silver bullet: toward a brighter future for system development
inferredcites →https://doi.org/10.1109/2.161283openalex-snapshot
Application graphics modeling support through object orientation
inferredcites →https://doi.org/10.1109/30.125072openalex-snapshot
The JPEG still picture compression standard
inferredcites →https://doi.org/10.1109/34.192463openalex-snapshot
A theory for multiresolution signal decomposition: the wavelet representation
inferredcites →https://doi.org/10.1109/35.46684openalex-snapshot
Visual telephony as an ISDN application
inferredcites →https://doi.org/10.1109/4.126536openalex-snapshot
A 100-MHz 2-D discrete cosine transform core processor
inferredcites →https://doi.org/10.1109/4.280685openalex-snapshot
The role of VLSI in multimedia
inferredcites →https://doi.org/10.1109/40.16792openalex-snapshot
Distributed fault-tolerant real-time systems: the Mars approach
inferredcites →https://doi.org/10.1109/40.210521openalex-snapshot
Research and development needs for advanced vehicle control systems
inferredcites →https://doi.org/10.1109/40.210523openalex-snapshot
Improving the reliability and safety of automotive electronics
inferredcites →https://doi.org/10.1109/40.216745openalex-snapshot
Architecture of the Pentium microprocessor
inferredcites →https://doi.org/10.1109/40.238002openalex-snapshot
The Power PC 601 microprocessor
inferredcites →https://doi.org/10.1109/40.248056openalex-snapshot
The development of ATM standards and technology: a retrospective
inferredcites →https://doi.org/10.1109/40.296153openalex-snapshot
Computer-aided hardware-software codesign
inferredcites →https://doi.org/10.1109/40.296154openalex-snapshot
Codesign of architectures for automotive powertrain modules
inferredcites →https://doi.org/10.1109/40.296155openalex-snapshot
Hardware-software codesign of embedded systems
inferredcites →https://doi.org/10.1109/40.296157openalex-snapshot
A software-hardware cosynthesis approach to digital system simulation
inferredcites →https://doi.org/10.1109/43.149767openalex-snapshot
Predicting system-level area and delay for pipelined and nonpipelined designs
inferredcites →https://doi.org/10.1109/43.277609openalex-snapshot
Formal verification of sequential hardware: a tutorial
inferredcites →https://doi.org/10.1109/43.285240openalex-snapshot
Estimating implementation bounds for real time DSP application specific circuits
inferredcites →https://doi.org/10.1109/49.219550openalex-snapshot
High-level software synthesis for the design of communication systems
inferredcites →https://doi.org/10.1109/5.293155openalex-snapshot
Hardware-software co-design of embedded systems
inferredcites →https://doi.org/10.1109/5.52214openalex-snapshot
The high-level synthesis of digital systems
inferredcites →https://doi.org/10.1109/52.88945openalex-snapshot
The Spring kernel: a new paradigm for real-time systems
inferredcites →https://doi.org/10.1109/54.232469openalex-snapshot
A hardware-software codesign methodology for DSP applications
inferredcites →https://doi.org/10.1109/54.232473openalex-snapshot
A case study in embedded-system design: The VuMan 2 wearable computer
inferredcites →https://doi.org/10.1109/54.245964openalex-snapshot
Hardware-software cosynthesis for microcontrollers
inferredcites →https://doi.org/10.1109/6.144508openalex-snapshot
How DEC developed Alpha
inferredcites →https://doi.org/10.1109/6.211957openalex-snapshot
Multimedia-the technology framework
inferredcites →https://doi.org/10.1109/6.211958openalex-snapshot
Multimedia-applications, implications
inferredcites →https://doi.org/10.1109/78.80854openalex-snapshot
A two-dimensional fast cosine transform algorithm based on Hou's approach
inferredcites →https://doi.org/10.1109/83.128028openalex-snapshot
Image coding based on a fractal theory of iterated contractive image transformations
inferredcites →https://doi.org/10.1109/83.136597openalex-snapshot
Image coding using wavelet transform
inferredcites →https://doi.org/10.1109/dac.1995.249979openalex-snapshot
Symbolic Modeling and Evaluation of Data Paths
inferredcites →https://doi.org/10.1109/edtc.1994.326902openalex-snapshot
Instruction-set matching and selection for DSP and ASIP code generation
inferredcites →https://doi.org/10.1109/hsc.1994.336705openalex-snapshot
CASTLE: an interactive environment for HW-SW co-design
inferredcites →https://doi.org/10.1109/hsc.1994.336718openalex-snapshot
An approach to the adaptation of estimated cost parameters in the COSYMA system
inferredcites →https://doi.org/10.1109/hsc.1994.336721openalex-snapshot
Design flow for hardware/software cosynthesis of a video compression system
inferredcites →https://doi.org/10.1109/hsc.1994.336723openalex-snapshot
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
inferredcites →https://doi.org/10.1109/hsc.1994.336724openalex-snapshot
A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem
inferredcites →https://doi.org/10.1109/hsc.1994.336725openalex-snapshot
Configuration-level hardware/software partitioning for real-time embedded systems
inferredcites →https://doi.org/10.1109/iccad.1988.122462openalex-snapshot
Combining event and data-flow graphs in behavioral synthesis
inferredcites →https://doi.org/10.1109/iccd.1993.393370openalex-snapshot
Design of the Intel Pentium processor
inferredcites →https://doi.org/10.1109/iccd.1993.393372openalex-snapshot
The PowerPC 601 design methodology
inferredcites →https://doi.org/10.1109/iccd.1994.331840openalex-snapshot
OK, if these CAD tools are so great, why isn't my chip design on schedule?
inferredcites →https://doi.org/10.1109/iccd.1994.331943openalex-snapshot
Design of an embedded video compression system-a quantitative approach
inferredcites →https://doi.org/10.1109/ishls.1994.302347openalex-snapshot
Data routing: a paradigm for efficient data-path synthesis and code generation
inferredcites →https://doi.org/10.1109/isscc.1995.535561openalex-snapshot
A single chip videophone video encoder/decoder
inferredcites →https://doi.org/10.1109/t-c.1974.223784openalex-snapshot
Discrete Cosine Transform
inferredcites →https://doi.org/10.1109/tc.1972.5009071openalex-snapshot
Some Computer Organizations and Their Effectiveness
inferredcites →https://doi.org/10.1109/tcad.1987.1270347openalex-snapshot
MIS: A Multiple-Level Logic Optimization System
inferredcites →https://doi.org/10.1109/tcom.1977.1093941openalex-snapshot
A Fast Computational Algorithm for the Discrete Cosine Transform
inferredcites →https://doi.org/10.1145/127601.127739openalex-snapshot
Cathedral-III
inferredcites →https://doi.org/10.1145/166266.166274openalex-snapshot
Performance of a software MPEG video decoder
inferredcites →https://doi.org/10.1145/217474.217596openalex-snapshot
Code optimization techniques for embedded DSP microprocessors
inferredcites →https://doi.org/10.1145/224486.224532openalex-snapshot
WWW based structuring of codesigns
inferredcites →https://doi.org/10.1145/357153.357155openalex-snapshot
Using Peephole Optimization on Intermediate Code
inferredcites →https://doi.org/10.1145/68182.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/70082.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1147/rd.341.0004openalex-snapshot
The evolution of RISC technology at IBM
inferredcites →https://doi.org/10.1201/9781003208938-1openalex-snapshot
Encyclopedia of Computer Science and Technology
inferredcites →https://doi.org/10.1524/itit.1993.35.2.4openalex-snapshot
Kompressionsalgorithmen für interaktive Multimedia- Systeme
inferredcites →https://doi.org/10.5555/191326.191503openalex-snapshot
Register assignrnent through resource classification for ASIP microcode generation
inferredcites →https://doi.org/10.5555/254208.254217openalex-snapshot
Data routing: a paradigm for efficient data-path synthesis and code generation
inferredcites →https://doi.org/10.5555/947185.947193openalex-snapshot
A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem
inferredcites →https://doi.org/10.5555/947185.947194openalex-snapshot
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
inferredcites →https://doi.org/10.5555/947185.947198openalex-snapshot
Design flow for hardware/software cosynthesis of a video compression system

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-45874-3_2openalex-snapshot
A Methodology to Design Programmable Embedded Systems
inferred← citeshttps://doi.org/10.1007/3-540-48753-0_30openalex-snapshot
Hw/Sw Codesign of Embedded Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-47721-8_14openalex-snapshot
An Energy-Efficient Reconfigurable Autoencoder Implementation on FPGA
inferred← citeshttps://doi.org/10.1007/978-3-319-05506-0_25openalex-snapshot
Design Support Tools of Cyber-Physical Systems
inferred← citeshttps://doi.org/10.1007/978-3-319-14254-8_25openalex-snapshot
Design Support Tools of Cyber-Physical Systems
inferred← citeshttps://doi.org/10.1007/978-3-319-18714-3_37openalex-snapshot
Extending Battery Management Systems for Making Informed Decisions on Battery Reuse
inferred← citeshttps://doi.org/10.1007/978-3-319-62569-0_8openalex-snapshot
I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems
inferred← citeshttps://doi.org/10.1007/978-3-7908-2127-7_11openalex-snapshot
Performance Optimizations in Embedded System Design
inferred← citeshttps://doi.org/10.1007/bfb0027799openalex-snapshot
Design and application of a light-weight persistency mechanism
inferred← citeshttps://doi.org/10.1007/s10207-025-01092-2openalex-snapshot
CARNYX: A framework for vulnerability detection via power consumption analysis in embedded systems
inferred← citeshttps://doi.org/10.1007/s10586-016-0597-2openalex-snapshot
Property preservation of refinement for Petri net based representation for embedded systems
inferred← citeshttps://doi.org/10.1016/j.cose.2025.104692openalex-snapshot
GJALLARHORN: A framework for vulnerability detection via electromagnetic side-channel analysis in embedded systems
inferred← citeshttps://doi.org/10.1016/j.vlsi.2009.06.002openalex-snapshot
Modern development methods and tools for embedded reconfigurable systems: A survey
inferred← citeshttps://doi.org/10.1016/s0141-9331(00)00100-9openalex-snapshot
A CASE-tool oriented approach for embedded systems design
inferred← citeshttps://doi.org/10.1016/s0950-5849(99)00072-5openalex-snapshot
Software intensive embedded systems
inferred← citeshttps://doi.org/10.1016/s1383-7621(03)00096-1openalex-snapshot
Modeling and formal verification of embedded systems based on a Petri net representation
inferred← citeshttps://doi.org/10.1016/s1383-7621(96)00063-xopenalex-snapshot
An approach to the design of RISC core processors for VLSI embedded systems
inferred← citeshttps://doi.org/10.1023/a:1008807631619openalex-snapshot
Retargetable Code Generation Based on Structural Processor Description
inferred← citeshttps://doi.org/10.1023/a:1008818711786openalex-snapshot
VLIW Processor Codesign for Video Processing
inferred← citeshttps://doi.org/10.1023/a:1008857008151openalex-snapshot
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
inferred← citeshttps://doi.org/10.1023/a:1008884219274openalex-snapshot
LYCOS: the Lyngby Co-Synthesis System
inferred← citeshttps://doi.org/10.1023/a:1008887603213openalex-snapshot
Prototyping of Tightly Coupled Hardware/Software-Systems
inferred← citeshttps://doi.org/10.1109/43.811318openalex-snapshot
Power optimization of variable-voltage core-based systems
inferred← citeshttps://doi.org/10.1109/5.558716openalex-snapshot
Embedded software in real-time signal processing systems: application and architecture trends
inferred← citeshttps://doi.org/10.1109/54.844335openalex-snapshot
A case study in design space exploration: the Tosca environment applied to a telecommunication link controller
inferred← citeshttps://doi.org/10.1109/access.2025.3577344openalex-snapshot
DS-HPPO Deep Reinforcement Learning for Optimal DVFS Control on an Image Signal Processor
inferred← citeshttps://doi.org/10.1109/asap.1997.606839openalex-snapshot
An approach for quantitative analysis of application-specific dataflow architectures
inferred← citeshttps://doi.org/10.1109/aspdac.1998.669502openalex-snapshot
A performance maximization algorithm to design ASIPs under the constraint of chip area including RAM and ROM sizes
inferred← citeshttps://doi.org/10.1109/ccece.1996.548062openalex-snapshot
Performance analysis for hardware/software co-synthesis
inferred← citeshttps://doi.org/10.1109/date.1998.655892openalex-snapshot
A system-level co-verification environment for ATM hardware design
inferred← citeshttps://doi.org/10.1109/dsd.2001.952119openalex-snapshot
Hierarchical modeling and verification of embedded systems
inferred← citeshttps://doi.org/10.1109/emscnt.1997.658457openalex-snapshot
An evaluation of an object-based technique for hardware/software codesign
inferred← citeshttps://doi.org/10.1109/eurdac.1996.558194openalex-snapshot
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs
inferred← citeshttps://doi.org/10.1109/hicss.1999.772879openalex-snapshot
Hardware/software codesign for FPGA-based systems
inferred← citeshttps://doi.org/10.1109/hsc.1997.584576openalex-snapshot
Design-for-debug in hardware/software co-design
inferred← citeshttps://doi.org/10.1109/hsc.1997.584593openalex-snapshot
Performance analysis in CoDe-X partitioning for structural programmable accelerators
inferred← citeshttps://doi.org/10.1109/hsc.1998.666241openalex-snapshot
Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models
inferred← citeshttps://doi.org/10.1109/hsc.1999.777432openalex-snapshot
System-level partitioning with uncertainty
inferred← citeshttps://doi.org/10.1109/icassp.2003.1202409openalex-snapshot
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III
inferred← citeshttps://doi.org/10.1109/iccd.1997.628901openalex-snapshot
Improving design turnaround time via two-levels HW/SW co-simulation
inferred← citeshttps://doi.org/10.1109/iccd.2000.878319openalex-snapshot
PEAS-III: an ASIP design environment
inferred← citeshttps://doi.org/10.1109/iciss.1997.630275openalex-snapshot
System-level power evaluation metrics
inferred← citeshttps://doi.org/10.1109/icm.1998.825581openalex-snapshot
A static method for system performance estimation
inferred← citeshttps://doi.org/10.1109/icme.2003.1220876openalex-snapshot
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III
inferred← citeshttps://doi.org/10.1109/iscas.1996.542083openalex-snapshot
Codesign of hardware, software, and algorithms-a case study
inferred← citeshttps://doi.org/10.1109/isss.1996.565877openalex-snapshot
A constructive method for exploiting code motion
inferred← citeshttps://doi.org/10.1109/isss.1998.730607openalex-snapshot
Data-path synthesis of VLIW video signal processors
inferred← citeshttps://doi.org/10.1109/iwrsp.1996.506734openalex-snapshot
HW/SW specification using OOM techniques
inferred← citeshttps://doi.org/10.1109/iwrsp.1999.779052openalex-snapshot
Model based multi-level prototyping
inferred← citeshttps://doi.org/10.1109/iwv.1998.667134openalex-snapshot
Cyclic process nets as a high-level behavioral specification model for embedded systems synthesis
inferred← citeshttps://doi.org/10.1109/sbcci.1998.715400openalex-snapshot
Hardware-software codesign of embedded systems
inferred← citeshttps://doi.org/10.1109/sbcci.2005.4286831openalex-snapshot
Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs
inferred← citeshttps://doi.org/10.1109/vl.1995.520803openalex-snapshot
Transforming SDL diagrams into a complete visual representation
inferred← citeshttps://doi.org/10.1145/1081081.1081100openalex-snapshot
Task sheduling for power optimisation of multi frequency synchronous data flow graphs
inferred← citeshttps://doi.org/10.1145/224486.224532openalex-snapshot
WWW based structuring of codesigns
inferred← citeshttps://doi.org/10.1145/238997.239002openalex-snapshot
A recursive technique for computing lower-bound performance of schedules
inferred← citeshttps://doi.org/10.1145/2738051openalex-snapshot
Dynamic Shared SPM Reuse for Real-Time Multicore Embedded Systems
inferred← citeshttps://doi.org/10.1145/277044.277088openalex-snapshot
Power optimization of variable voltage core-based systems
inferred← citeshttps://doi.org/10.1145/301177.301531openalex-snapshot
System-level partitioning with uncertainty
inferred← citeshttps://doi.org/10.1145/329458.329461openalex-snapshot
A code-motion pruning technique for global scheduling
inferred← citeshttps://doi.org/10.1145/3579028.3609005openalex-snapshot
A configurable approach to cyber-physical systems fuzzing
inferred← citeshttps://doi.org/10.1201/9781420037203.ch19openalex-snapshot
Design of Low-Power Processor Cores Using a Retargetable Tool Flow
inferred← citeshttps://doi.org/10.3233/ica-1998-5104openalex-snapshot
Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach
inferred← citeshttps://doi.org/10.3233/ica-1998-5106openalex-snapshot
Hardware/Software Co-Design Methodology for Design of Embedded Systems
inferred← citeshttps://doi.org/10.4018/978-1-4666-0912-9.ch001openalex-snapshot
Current Challenges in Embedded Communication Systems
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Current Challenges in Embedded Communication Systems
inferred← citeshttps://doi.org/10.4236/am.2013.41021openalex-snapshot
A Water-Saving Technique Using Embedded System
inferred← citeshttps://doi.org/10.5121/csit.2011.1315openalex-snapshot
Embedded Intensive Patient Care Unit
inferred← citeshttps://doi.org/10.5121/ijesa.2011.1205openalex-snapshot
Embedded Patient Monitoring System
inferred← citeshttps://doi.org/10.5555/252471.252499openalex-snapshot
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs
inferred← citeshttps://doi.org/10.5555/278241.278302openalex-snapshot
Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models
inferred← citeshttps://doi.org/10.5555/293016.293036openalex-snapshot
Data-path synthesis of VLIW video signal processors
inferred← citeshttps://doi.org/10.5555/368058.368257openalex-snapshot
A system-level co-verification environment for ATM hardware design
inferred← citeshttps://doi.org/10.5555/524431.857925openalex-snapshot
A constructive method for exploiting code motion
inferred← citeshttps://doi.org/10.5555/552517.829462openalex-snapshot
Hardware-software codesign of embedded systems
inferred← citeshttps://doi.org/10.5555/792768.793509openalex-snapshot
Performance analysis in CoDe-X partitioning for structural programmable accelerators
inferred← citeshttps://doi.org/10.5753/wei.2026.22695openalex-snapshot
Embedded Systems Training: Experiences, Results, and Lessons Learned
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.