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Rate-optimal schedule for multi-rate DSP computations

https://doi.org/10.1007/bf02407086
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-06859-7_145openalex-snapshot
First version of a data flow procedure language
inferredcites →https://doi.org/10.1007/3-540-55599-4_112openalex-snapshot
Minimizing loop storage allocation for an argument-fetching dataflow architecture model
inferredcites →https://doi.org/10.1007/3-540-55895-0_462openalex-snapshot
A polynomial time method for optimal software pipelining
inferredcites →https://doi.org/10.1007/3-540-55984-1_17openalex-snapshot
A register allocation framework based on hierarchical cyclic interval graphs
inferredcites →https://doi.org/10.1007/3-540-57208-2_26openalex-snapshot
Minimal memory schedules for dataflow networks
inferredcites →https://doi.org/10.1007/978-3-642-95432-0_7openalex-snapshot
Optimizing Synchronous Circuitry by Retiming (Preliminary Version)
inferredcites →https://doi.org/10.1007/bf00129781openalex-snapshot
Fine-grain compilation for pipelined machines
inferredcites →https://doi.org/10.1007/bf02120034openalex-snapshot
Resource constrained scheduling of uniform algorithms
inferredcites →https://doi.org/10.1016/0012-365x(78)90011-0openalex-snapshot
A characterization of the minimum cycle mean in a digraph
inferredcites →https://doi.org/10.1016/0096-0551(81)90048-5openalex-snapshot
Register allocation via coloring
inferredcites →https://doi.org/10.1109/12.102826openalex-snapshot
Compile-time scheduling and assignment of data-flow program graphs with data-dependent iteration
inferredcites →https://doi.org/10.1109/12.73588openalex-snapshot
Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding
inferredcites →https://doi.org/10.1109/29.46557openalex-snapshot
Gabriel: a design environment for DSP
inferredcites →https://doi.org/10.1109/71.89067openalex-snapshot
Consistency in dataflow graphs
inferredcites →https://doi.org/10.1109/92.273152openalex-snapshot
Rate-optimal DSP synthesis by pipeline and minimum unfolding
inferredcites →https://doi.org/10.1109/asap.1992.218536openalex-snapshot
High level software synthesis for signal processing systems
inferredcites →https://doi.org/10.1109/asap.1993.397118openalex-snapshot
Resource constrained scheduling of uniform algorithm
inferredcites →https://doi.org/10.1109/cicc.1993.590480openalex-snapshot
Generalized ILP scheduling and allocation for high-level DSP synthesis
inferredcites →https://doi.org/10.1109/glsv.1993.224475openalex-snapshot
Rate-optimal static scheduling for DSP data-flow programs
inferredcites →https://doi.org/10.1109/icassp.1992.226558openalex-snapshot
Well-behaved dataflow programs for DSP computation
inferredcites →https://doi.org/10.1109/icassp.1992.226560openalex-snapshot
Direct synthesis of optimized DSP assembly code from signal flow block diagrams
inferredcites →https://doi.org/10.1109/tc.1987.5009446openalex-snapshot
Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing
inferredcites →https://doi.org/10.1109/tse.1980.230492openalex-snapshot
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
inferredcites →https://doi.org/10.1117/12.962367openalex-snapshot
Automatic Mapping Of Large Signal Processing Systems To A Parallel Machine
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/113445.113463openalex-snapshot
A timed Petri-net model for fine-grain loop scheduling
inferredcites →https://doi.org/10.1145/113446.113463openalex-snapshot
A timed Petri-net model for fine-grain loop scheduling
inferredcites →https://doi.org/10.1145/123465.123481openalex-snapshot
Software pipelining
inferredcites →https://doi.org/10.1145/158511.158519openalex-snapshot
A novel framework of register allocation for software pipelining
inferredcites →https://doi.org/10.1145/255305.255317openalex-snapshot
A compilation technique for software pipelining of loops with conditional jumps
inferredcites →https://doi.org/10.1145/2591635.2667160openalex-snapshot
Aglobalresource-constrained parallelization technique
inferredcites →https://doi.org/10.1145/318789.318807openalex-snapshot
A global resource-constrained parallelization technique
inferredcites →https://doi.org/10.1145/321479.321485openalex-snapshot
Scheduling Parallel Computations
inferredcites →https://doi.org/10.1145/502874.502879openalex-snapshot
A Fortran compiler for the FPS-164 scientific computer
inferredcites →https://doi.org/10.1145/53990.54021openalex-snapshot
Optimal loop parallelization
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/960116.54021openalex-snapshot
Optimal loop parallelization
inferredcites →https://doi.org/10.1145/960116.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/989393.989420openalex-snapshot
Software pipelining

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4419-6400-7_2openalex-snapshot
Formal Modeling of Embedded Systems with Explicit Schedules and Routes
inferred← citeshttps://doi.org/10.1007/978-3-642-05356-6_5openalex-snapshot
Eigenschaftsprüfung
inferred← citeshttps://doi.org/10.1007/978-3-642-24310-3_5openalex-snapshot
Performance Model Checking Scenario-Aware Dataflow
inferred← citeshttps://doi.org/10.1007/s10626-019-00278-wopenalex-snapshot
An improved approach for marking optimization of timed weighted marked graphs
inferred← citeshttps://doi.org/10.1016/j.dam.2008.03.018openalex-snapshot
Periodic schedules for linear precedence constraints
inferred← citeshttps://doi.org/10.1016/j.ejor.2008.07.037openalex-snapshot
A sufficient condition for the liveness of weighted event graphs
inferred← citeshttps://doi.org/10.1023/a:1015452903532openalex-snapshot
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
inferred← citeshttps://doi.org/10.1109/acsd.2006.33openalex-snapshot
Throughput Analysis of Synchronous Data Flow Graphs
inferred← citeshttps://doi.org/10.1109/aiccsa.2010.5586972openalex-snapshot
A new approach for minimizing buffer capacities with throughput constraint for embedded system design
inferred← citeshttps://doi.org/10.1109/aspdac.2007.358032openalex-snapshot
Retiming for Synchronous Data Flow Graphs
inferred← citeshttps://doi.org/10.1109/ccgrid.2010.114openalex-snapshot
Bandwidth Allocation for Iterative Data-Dependent E-science Applications
inferred← citeshttps://doi.org/10.1109/date.2012.6176645openalex-snapshot
Combining module selection and replication for throughput-driven streaming programs
inferred← citeshttps://doi.org/10.1109/iccie.2009.5223822openalex-snapshot
A polynomial algorithm for the computation of buffer capacities with throughput constraint for embedded system design
inferred← citeshttps://doi.org/10.1109/memcod.2016.7797751openalex-snapshot
Specification of precise timing in synchronous dataflow models
inferred← citeshttps://doi.org/10.1109/rtas.2012.15openalex-snapshot
Static Rate-Optimal Scheduling of Multirate DSP Algorithms via Retiming and Unfolding
inferred← citeshttps://doi.org/10.1109/rtcsa.1997.629225openalex-snapshot
Real-time scheduling in a programmable radar signal processor
inferred← citeshttps://doi.org/10.1109/tac.2012.2191871openalex-snapshot
Periodic Schedules for Bounded Timed Weighted Event Graphs
inferred← citeshttps://doi.org/10.1109/tcad.2015.2495167openalex-snapshot
Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding
inferred← citeshttps://doi.org/10.1145/1629911.1630146openalex-snapshot
Reduction techniques for synchronous dataflow graphs
inferred← citeshttps://doi.org/10.1145/951710.951721openalex-snapshot
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
inferred← citeshttps://doi.org/10.5555/2492708.2492962openalex-snapshot
Combining module selection and replication for throughput-driven streaming programs
inferred← citeshttps://doi.org/10.6100/ir635718openalex-snapshot
Timing analysis of synchronous data flow graphs
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