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Reducing division latency with reciprocal caches

https://doi.org/10.1007/bf02425917
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/arith.1993.378089openalex-snapshot
Exploiting trivial and redundant computation
inferredcites →https://doi.org/10.1109/t-c.1970.223019openalex-snapshot
On Division by Functional Iteration
inferredcites →https://doi.org/10.1145/178243.178260openalex-snapshot
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What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/scj.10498openalex-snapshot
Combining variable latency pipeline with instruction reuse for execution latency reduction
inferred← citeshttps://doi.org/10.1007/978-3-642-00904-4_13openalex-snapshot
Reexecution and Selective Reuse in Checkpoint Processors
inferred← citeshttps://doi.org/10.1109/acssc.2002.1197047openalex-snapshot
Reducing the latency of division operations with partial caching
inferred← citeshttps://doi.org/10.1109/arith.1997.614891openalex-snapshot
The SNAP project: design of floating point arithmetic units
inferred← citeshttps://doi.org/10.1109/dsd.2009.209openalex-snapshot
Instruction Precomputation for Fault Detection
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00017openalex-snapshot
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
inferred← citeshttps://doi.org/10.1109/micro.2010.41openalex-snapshot
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
inferred← citeshttps://doi.org/10.1109/siphotonics.2015.11openalex-snapshot
Optimal Power Efficient Photonic SWMR Buses
inferred← citeshttps://doi.org/10.1145/291006.291056openalex-snapshot
Accelerating multi-media processing by implementing memoing in multiplication and division units
inferred← citeshttps://doi.org/10.1145/291069.291056openalex-snapshot
Accelerating multi-media processing by implementing memoing in multiplication and division units
inferred← citeshttps://doi.org/10.1145/384265.291056openalex-snapshot
Accelerating multi-media processing by implementing memoing in multiplication and division units
inferred← citeshttps://doi.org/10.2312/eggh/eggh96/049-058openalex-snapshot
The Setup for Triangle Rasterization
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93303openalex-snapshot
Microarchitectural Techniques to Exploit Repetitive Computations and Values
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