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Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Reexecution and Selective Reuse in Checkpoint Processors
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Reducing division latency with reciprocal caches
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Godson-T: An Efficient Many-Core Architecture for Parallel Program Executions
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STEPS Towards Cache-Resident Transaction Processing
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Exploiting trivial and redundant computation
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A compiler scheme for reusing intermediate computation results
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Enhancing speedup in network processing applications by exploiting instruction reuse with flow aggregation
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Exploiting basic block value locality with block reuse
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Profiling driven computation reuse: an embedded software synthesis technique for energy and performance optimization
inferredcites →https://doi.org/10.1109/iedm.2005.1609253openalex-snapshot
Scaling, power, and the future of CMOS
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The SPLASH-2 programs: characterization and methodological considerations
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Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2004.1310789openalex-snapshot
A complexity-effective approach to ALU bandwidth enhancement for instruction-level temporal redundancy
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2006.17openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/l-ca.2005.1openalex-snapshot
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
inferredcites →https://doi.org/10.1109/micro.1998.742782openalex-snapshot
Understanding the differences between value prediction and instruction reuse
inferredcites →https://doi.org/10.1109/micro.2006.10openalex-snapshot
ASR: Adaptive Selective Replication for CMP Caches
inferredcites →https://doi.org/10.1109/pact.1998.727185openalex-snapshot
Dynamic elimination of pointer-expressions
inferredcites →https://doi.org/10.1109/pact.2000.888334openalex-snapshot
The dynamic trace memoization reuse technique
inferredcites →https://doi.org/10.1109/pact.2000.888335openalex-snapshot
Exploring sub-block value reuse for superscalar processors
inferredcites →https://doi.org/10.1109/sbac-pad.2004.42openalex-snapshot
Value Predictors for Reuse through Speculation on Traces
inferredcites →https://doi.org/10.1145/1028176.1006732openalex-snapshot
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/263272.263348openalex-snapshot
Low power data processing by elimination of redundant computations
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
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Accelerating multi-media processing by implementing memoing in multiplication and division units
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An empirical analysis of instruction repetition
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Dynamic removal of redundant computations
inferredcites →https://doi.org/10.1145/503272.503296openalex-snapshot
Adaptive functional programming
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An architectural alternative to optimizing compilers
inferredcites →https://doi.org/10.5555/290940.290983openalex-snapshot
Understanding the differences between value prediction and instruction reuse
inferredcites →https://doi.org/10.5555/517554.825776openalex-snapshot
Exploring Sub-Block Value Reuse for Superscalar Processors
inferredcites →https://doi.org/10.5555/517554.825778openalex-snapshot
The Dynamic Trace Memorization Reuse Technique
inferredcites →https://doi.org/10.5555/522344.825668openalex-snapshot
Dynamic elimination of pointer-expressions
inferredcites →https://doi.org/10.5555/789083.1022820openalex-snapshot
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
inferredcites →https://doi.org/10.5555/977395.977679openalex-snapshot
A compiler scheme for reusing intermediate computation results
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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New Methodologies for Parallel Architecture
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Highly Optimized Code Generation for Stencil Codes with Computation Reuse for GPUs
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.11.006openalex-snapshot
DITVA: Dynamic Inter-Thread Vectorization Architecture
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.10.001openalex-snapshot
A resource utilization based instruction fetch policy for SMT processors
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.09.007openalex-snapshot
BRAM-based function reuse for multi-core architectures in FPGAs
inferred← citeshttps://doi.org/10.1016/j.parco.2014.03.006openalex-snapshot
Thread scheduling and memory coalescing for dynamic vectorization of SPMD workloads
inferred← citeshttps://doi.org/10.1109/dsn.2012.6263959openalex-snapshot
BLOCKWATCH: Leveraging similarity in parallel programs for error detection
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Simultaneous branch and warp interweaving for sustained GPU performance
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Execution Drafting: Energy Efficiency through Computation Deduplication
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big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
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Data and Instruction Uniformity in Minimal Multi-threading
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Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP
inferred← citeshttps://doi.org/10.1109/tc.2017.2770126openalex-snapshot
Simultaneous and Speculative Thread Migration for Improving Energy Efficiency of Heterogeneous Core Architectures
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Simultaneous branch and warp interweaving for sustained GPU performance
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Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement
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Microarchitectural mechanisms to exploit value structure in SIMT architectures
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Microarchitectural mechanisms to exploit value structure in SIMT architectures
inferred← citeshttps://doi.org/10.1145/3033019.3033024openalex-snapshot
Compile-time function memoization
inferred← citeshttps://doi.org/10.1145/3373376.3378520openalex-snapshot
Dimensionality-Aware Redundant SIMT Instruction Elimination
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R2D2: Removing ReDunDancy Utilizing Linearity of Address Generation in GPUs
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inferred← citeshttps://doi.org/10.70675/67734194z7badz4c74z81afzd975dfd0dc6fopenalex-snapshot
Intercepting functions for memoization
inferred← citeshttps://doi.org/10.70675/cf508f02z8d3dz419ezaf16z55d93104a2e6openalex-snapshot
Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread
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