On the public citation graph
Specification of software pipelining using petri nets
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-72521-3openalex-snapshot
Languages and compilers for parallel computing : 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006 : revised papers
inferredcites →https://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferredcites →https://doi.org/10.1109/32.6136openalex-snapshot
A development environment for horizontal microcode
inferredcites →https://doi.org/10.1109/iscas.1992.230669openalex-snapshot
An environment for the development of microcode for pipelined architectures
inferredcites →https://doi.org/10.1109/micro.1990.151426openalex-snapshot
Software pipelining: a comparison and improvement
inferredcites →https://doi.org/10.1109/micro.1992.697012openalex-snapshot
Code Generation Schema For Modulo Scheduled Loops
inferredcites →https://doi.org/10.1145/113446.113463openalex-snapshot
A timed Petri-net model for fine-grain loop scheduling
inferredcites →https://doi.org/10.1145/144965.145795openalex-snapshot
Code generation schema for modulo scheduled loops
inferredcites →https://doi.org/10.1145/144965.145797openalex-snapshot
A dynamic-programming technique for compacting loops
inferredcites →https://doi.org/10.1145/960116.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.5555/255237.255248openalex-snapshot
Software pipelining: a comparison and improvement
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/(sici)1097-024x(199803)28:3<249::aid-spe152>3.0.co;2-xopenalex-snapshot
Building a retargetable local instruction scheduler
inferred← citeshttps://doi.org/10.1007/3-540-44905-1_26openalex-snapshot
Loop Shifting for Loop Compaction
inferred← citeshttps://doi.org/10.1023/a:1007506711786openalex-snapshot
Loop Shifting for Loop Compaction
inferred← citeshttps://doi.org/10.1109/icapp.1996.562903openalex-snapshot
A generalized stochastic Petri net approach for modeling multiprocessor parallel processing systems
inferred← citeshttps://doi.org/10.1109/micro.1995.476817openalex-snapshot
Petri net versus module scheduling for software pipelining
inferred← citeshttps://doi.org/10.1145/1366230.1366267openalex-snapshot
Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture
inferred← citeshttps://doi.org/10.1145/1982185.1982329openalex-snapshot
Petri net based performance modeling for effective DVFS for multithreaded programs
inferred← citeshttps://doi.org/10.1145/2016604.2016654openalex-snapshot
Evaluation of dynamic voltage and frequency scaling for stream programs
inferred← citeshttps://doi.org/10.5555/225160.225179openalex-snapshot
Petri net versus module scheduling for software pipelining
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