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Decomposed software pipelining: A new perspective and a new approach
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-19027-9_15openalex-snapshot
Perfect pipelining: A new loop parallelization technique
inferredcites →https://doi.org/10.1007/3-540-55895-0_462openalex-snapshot
A polynomial time method for optimal software pipelining
inferredcites →https://doi.org/10.1007/3-540-55895-0_463openalex-snapshot
Scheduling loops on parallel processors: A simple algorithm with close to optimum performance
inferredcites →https://doi.org/10.1007/978-1-4613-1705-0openalex-snapshot
A Systolic Array Optimizing Compiler
inferredcites →https://doi.org/10.1016/0166-218x(81)90026-3openalex-snapshot
Parametric shortest path algorithms with an application to cyclic staffing
inferredcites →https://doi.org/10.1016/0166-218x(94)00102-jopenalex-snapshot
A study of the cyclic scheduling problem on parallel processors
inferredcites →https://doi.org/10.1051/ro/1991250201611openalex-snapshot
Résolution d'un problème d'ordonnancement cyclique à itérations indépendantes et contraintes de ressources
inferredcites →https://doi.org/10.1109/c-m.1981.220595openalex-snapshot
An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family
inferredcites →https://doi.org/10.1109/micro.1990.151427openalex-snapshot
Using a lookahead window in a compaction-based parallelizing compiler
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/1096503.1096504openalex-snapshot
Using a lookahead window in a compaction-based parallelizing compiler
inferredcites →https://doi.org/10.1145/113445.113463openalex-snapshot
A timed Petri-net model for fine-grain loop scheduling
inferredcites →https://doi.org/10.1145/121973.773543openalex-snapshot
Book review: Highly Parallel Computing by George Almasi and Allan Gotlieb (Benjamin/Cummings, 1989)
inferredcites →https://doi.org/10.1145/155090.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferredcites →https://doi.org/10.1145/173262.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferredcites →https://doi.org/10.1145/17356.17401openalex-snapshot
Highly concurrent scalar processing
inferredcites →https://doi.org/10.1145/19530.19541openalex-snapshot
URPR—An extension of URCR for software pipelining
inferredcites →https://doi.org/10.1145/19551.19541openalex-snapshot
URPR—An extension of URCR for software pipelining
inferredcites →https://doi.org/10.1145/255305.255317openalex-snapshot
A compilation technique for software pipelining of loops with conditional jumps
inferredcites →https://doi.org/10.1145/502874.502879openalex-snapshot
A Fortran compiler for the FPS-164 scientific computer
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/0-306-48706-3_13openalex-snapshot
Application-Domain-Driven System Design for Pervasive Video Processing
inferred← citeshttps://doi.org/10.1007/3-540-44905-1_26openalex-snapshot
Loop Shifting for Loop Compaction
inferred← citeshttps://doi.org/10.1007/3-540-61053-7_49openalex-snapshot
Pipelining-dovetailing: A transformation to enhance software pipelining for nested loops
inferred← citeshttps://doi.org/10.1007/978-3-642-13374-9_19openalex-snapshot
Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops
inferred← citeshttps://doi.org/10.1007/bfb0002894openalex-snapshot
OCEANS: Optimizing compilers for embedded applications
inferred← citeshttps://doi.org/10.1007/bfb0026433openalex-snapshot
A new fast algorithm for optimal register allocation in modulo scheduled loops
inferred← citeshttps://doi.org/10.1007/bfb0057974openalex-snapshot
OCEANS: Optimising compilers for embedded applicatioNS
inferred← citeshttps://doi.org/10.1007/s10766-012-0203-zopenalex-snapshot
Minimal Unroll Factor for Code Generation of Software Pipelining
inferred← citeshttps://doi.org/10.1007/s10951-010-0220-yopenalex-snapshot
Worst case analysis of decomposed software pipelining for cyclic unitary RCPSP with precedence delays
inferred← citeshttps://doi.org/10.1007/s10951-014-0399-4openalex-snapshot
The impact of core precedences in a cyclic RCPSP with precedence delays
inferred← citeshttps://doi.org/10.1023/a:1007506711786openalex-snapshot
Loop Shifting for Loop Compaction
inferred← citeshttps://doi.org/10.1109/12.689643openalex-snapshot
Modulo scheduling with reduced register pressure
inferred← citeshttps://doi.org/10.1109/12.910814openalex-snapshot
Lifetime-sensitive modulo scheduling in a production environment
inferred← citeshttps://doi.org/10.1109/71.655240openalex-snapshot
Circuit retiming applied to decomposed software pipelining
inferred← citeshttps://doi.org/10.1109/icassp.2003.1202338openalex-snapshot
De-pipeline a software-pipelined loop
inferred← citeshttps://doi.org/10.1109/micro.1994.717421openalex-snapshot
Software pipelining with register allocation and spilling
inferred← citeshttps://doi.org/10.1109/micro.1995.476843openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferred← citeshttps://doi.org/10.1109/pact.1996.554030openalex-snapshot
Swing Modulo Scheduling: A Lifetime-Sensitive Approach
inferred← citeshttps://doi.org/10.1109/scam.2004.20openalex-snapshot
Software de-pipelining technique
inferred← citeshttps://doi.org/10.1109/tc.2007.70752openalex-snapshot
On Periodic Register Need in Software Pipelining
inferred← citeshttps://doi.org/10.1109/tvlsi.2002.1043323openalex-snapshot
Hardware-software partitioning and pipelined scheduling of transformative applications
inferred← citeshttps://doi.org/10.1145/1839480.1839485openalex-snapshot
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
inferred← citeshttps://doi.org/10.1145/192724.192734openalex-snapshot
Software pipelining with register allocation and spilling
inferred← citeshttps://doi.org/10.1145/2043662.2043671openalex-snapshot
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors
inferred← citeshttps://doi.org/10.1145/237578.237613openalex-snapshot
A new guaranteed heuristic for the software pipelining problem
inferred← citeshttps://doi.org/10.1145/2540708.2540738openalex-snapshot
Allocating rotating registers by scheduling
inferred← citeshttps://doi.org/10.1145/2544137.2544148openalex-snapshot
Just-In-Time Software Pipelining
inferred← citeshttps://doi.org/10.1145/2581122.2544148openalex-snapshot
Just-In-Time Software Pipelining
inferred← citeshttps://doi.org/10.1201/9781420043839.ch20openalex-snapshot
Advances in Software Pipelining
inferred← citeshttps://doi.org/10.5281/zenodo.38525openalex-snapshot
Loop Optimization With Tradeoff Between Cycle Count And Code Size For Dsp Applications
inferred← citeshttps://doi.org/10.5555/224659.224940openalex-snapshot
Decomposed software pipelining with reduced register requirement
inferred← citeshttps://doi.org/10.5555/225160.225210openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferred← citeshttps://doi.org/10.70675/7aef2368z3e6cz4ce2z9827z502a3dd630d6openalex-snapshot
From Cyclo-Static Process Networks to Code Generation for Multidimensional Software Pipelining
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