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Compiling for the Cydra

https://doi.org/10.1007/bf01205184
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4613-1705-0openalex-snapshot
A Systolic Array Optimizing Compiler
inferredcites →https://doi.org/10.1007/bf00127840openalex-snapshot
Parallelization of WHILE loops on pipelined architectures
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1007/bf01205183openalex-snapshot
The cydra 5 minisupercomputer: Architecture and implementation
inferredcites →https://doi.org/10.1007/bfb0038668openalex-snapshot
Data flow and dependence analysis for instruction level parallelism
inferredcites →https://doi.org/10.1080/00207168208803296openalex-snapshot
A composite hoisting-strength reduction transformation for global program optimization part I
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/c-m.1981.220595openalex-snapshot
An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1137/0205007openalex-snapshot
On Algorithms for Enumerating All Circuits of a Graph
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/1014194.800930openalex-snapshot
MIPS
inferredcites →https://doi.org/10.1145/1067649.801721openalex-snapshot
Efficient code generation for horizontal architectures
inferredcites →https://doi.org/10.1145/143095.143141openalex-snapshot
Register allocation for software pipelined loops
inferredcites →https://doi.org/10.1145/17356.17401openalex-snapshot
Highly concurrent scalar processing
inferredcites →https://doi.org/10.1145/285930.285985openalex-snapshot
Very long instruction work architectures and the ELI-512
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/362814.362819openalex-snapshot
An efficient search algorithm to find the elementary circuits of a graph
inferredcites →https://doi.org/10.1145/502874.502879openalex-snapshot
A Fortran compiler for the FPS-164 scientific computer
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/73560.73562openalex-snapshot
Global value numbers and redundant computations
inferredcites →https://doi.org/10.1145/93542.93553openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Static Analysis for Guarded Code
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Speculative Prefetching of Induction Pointers
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A unified software pipeline construction scheme for modulo scheduled loops
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Instruction-Level Parallel Processing: History, Overview, and Perspective
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The Cydra 5 Minisupercomputer: Architecture and Implementation
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Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors
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Resource Usage Modelling for Software Pipelining
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Extending Modulo Scheduling with Memory Reference Merging
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Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation
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Instruction-level parallel processing: History, overview, and perspective
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The cydra 5 minisupercomputer: Architecture and implementation
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Decomposed software pipelining: A new perspective and a new approach
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Iterative Modulo Scheduling
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Parallelization of Control Recurrences for ILP Processors
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Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling
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An experimental study of an ILP-based exact solution method for software pipelining
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Parametric computation of margins and of minimum cumulative register lifetime dates
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A new fast algorithm for optimal register allocation in modulo scheduled loops
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A unified software pipeline construction scheme for modulo scheduled loops
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Minimal Unroll Factor for Code Generation of Software Pipelining
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CP-PACS: A massively parallel processor at the University of Tsukuba
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Machine-Description Driven Compilers for EPIC and VLIW Processors
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A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors
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Quantitative Evaluation of Register Pressure on Software Pipelined Loops
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Meld Scheduling: A Technique for Relaxing Scheduling Constraints
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Modulo scheduling without overlapped lifetimes
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Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures
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Modulo scheduling without overlapped lifetimes
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Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures
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Lifetime-sensitive modulo scheduling
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Lifetime-sensitive modulo scheduling
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Height reduction of control recurrences for ILP processors
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Iterative modulo scheduling
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Minimizing register requirements under resource-constrained rate-optimal software pipelining
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Scheduling and mapping
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Software pipelining
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Scheduling and mapping
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Software pipelining showdown
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A reduced multipipeline machine description that preserves scheduling constraints
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Software pipelining showdown
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A reduced multipipeline machine description that preserves scheduling constraints
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Allocating rotating registers by scheduling
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Efficient formulation for optimal modulo schedulers
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Efficient formulation for optimal modulo schedulers
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Optimum modulo schedules for minimum register requirements
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Increasing memory bandwidth with wide buses
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Resource widening versus replication
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Control CPR
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Control CPR
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Resource usage models for instruction scheduling
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Modulo scheduling for the TMS320C6x VLIW DSP architecture
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Modulo scheduling for the TMS320C6x VLIW DSP architecture
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Improved spill code generation for software pipelined loops
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Communication scheduling
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Improved spill code generation for software pipelined loops
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An integrated approach to accelerate data and predicate computations in hyperblocks
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Two-level hierarchical register file organization for VLIW processors
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Communication scheduling
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Communication scheduling
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ILP-based Instruction Scheduling for IA-64
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ILP-based Instruction Scheduling for IA-64
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ILP-based Instruction Scheduling for IA-64
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Communication scheduling
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On achieving balanced power consumption in software pipelined loops
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Branch Predication
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Power Aware Embedded Computing
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Power Aware Embedded Computing
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Instruction Scheduling
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Instruction Scheduling
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Advances in Software Pipelining
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Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor
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Design and Implementation of a Framework for Integrating Front-End and Back-End Compilers
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Load scheduling: reducing pressure on distributed register files for free
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Efficient instruction scheduling using finite state automata
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Modulo scheduling with multiple initiation intervals
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Register allocation for predicated code
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Unrolling-based optimizations for modulo scheduling
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Stage scheduling: a technique to reduce the register requirements of a module schedule
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Hypernode reduction modulo scheduling
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Profile-driven instruction level parallel scheduling with application to super blocks
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Analysis techniques for predicated code
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Heuristics for register-constrained software pipelining
inferred← citeshttps://doi.org/10.5555/243846.243893openalex-snapshot
Software pipelining loops with conditional branches
inferred← citeshttps://doi.org/10.5555/243846.243903openalex-snapshot
Meld scheduling: relaxing scheduling constraints across region boundaries
inferred← citeshttps://doi.org/10.5555/243846.243909openalex-snapshot
Optimization of machine descriptions for efficient use
inferred← citeshttps://doi.org/10.5555/255235.255243openalex-snapshot
GPMB—software pipelining branch-intensive loops
inferred← citeshttps://doi.org/10.5555/290940.290990openalex-snapshot
Widening resources: a cost-effective technique for aggressive ILP architectures
inferred← citeshttps://doi.org/10.5555/517554.825772openalex-snapshot
Efficient Backtracking Instruction Schedulers
inferred← citeshttps://doi.org/10.5555/563998.564020openalex-snapshot
Modulo scheduling with integrated register spilling for clustered VLIW architectures
inferred← citeshttps://doi.org/10.5555/774861.774873openalex-snapshot
Reduced code size modulo scheduling in the absence of hardware support
inferred← citeshttps://doi.org/10.5555/776261.776276openalex-snapshot
Inlining of mathematical functions in HP-UX for Itanium® 2
inferred← citeshttps://doi.org/10.5555/942806.943828openalex-snapshot
Efficient resource management during instruction scheduling for the EPIC architectures
inferred← citeshttps://doi.org/10.5555/977395.977656openalex-snapshot
Code generation for single-dimension software pipelining of multi-dimensional loops
inferred← citeshttps://doi.org/10.5753/sbac-pad.2001.22210openalex-snapshot
Using the SGI Pro64 Open Source Compiler Infra-Structure for Teaching and Research
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93312openalex-snapshot
Recursos anchos: una técnica de bajo coste para explotar paralelismo agresivo en códigos numéricos
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93313openalex-snapshot
Loop pipelining with resource and timing constraints
inferred← citeshttps://doi.org/10.6100/ir808001openalex-snapshot
Compiler Strategies for Transport Triggered Architectures.
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