On the public citation graph
The M-machine multicomputer
0 signed · 105 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-3604-8_13openalex-snapshot
The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot
Introduction to V.L.S.I. Systems
inferredcites →https://doi.org/10.1109/2.84896openalex-snapshot
Computer technology and architecture: an evolving interaction
inferredcites →https://doi.org/10.1109/ipps.1991.153792openalex-snapshot
Prototype implementation of a highly parallel dataflow machine EM-4
inferredcites →https://doi.org/10.1109/isca.1988.5255openalex-snapshot
MASA: a multithreaded processor architecture for parallel symbolic computing
inferredcites →https://doi.org/10.1109/mdt.1987.295211openalex-snapshot
MARS: A Multiprocessor-Based Programmable Accelerator
inferredcites →https://doi.org/10.1109/superc.1990.130118openalex-snapshot
Architecture and implementation of a VLIW supercomputer
inferredcites →https://doi.org/10.1117/12.932535openalex-snapshot
Architecture And Applications Of The HEP Multiprocessor Computer System
inferredcites →https://doi.org/10.1145/106974.106976openalex-snapshot
A variable instruction stream extension to the VLIW architecture
inferredcites →https://doi.org/10.1145/143365.143497openalex-snapshot
A tightly-coupled processor-network interface
inferredcites →https://doi.org/10.1145/192007.192056openalex-snapshot
The Stanford FLASH multiprocessor
inferredcites →https://doi.org/10.1145/195473.195579openalex-snapshot
Hardware support for fast capability-based addressing
inferredcites →https://doi.org/10.1145/325096.325116openalex-snapshot
Supporting systolic and memory communication in iWarp
inferredcites →https://doi.org/10.1145/74925.74956openalex-snapshot
Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results
inferredcites →https://doi.org/10.1145/74926.74956openalex-snapshot
Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results
inferredcites →https://doi.org/10.1147/rd.111.0025openalex-snapshot
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
inferredcites →https://doi.org/10.21236/ada211909openalex-snapshot
The J-Machine: A Fine Grain Concurrent Computer
inferredcites →https://doi.org/10.5555/110382.110622openalex-snapshot
Architecture and implementation of a VLIW supercomputer
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.755openalex-snapshot
Towards a more realistic comparative analysis of multicomputer networks
inferred← citeshttps://doi.org/10.1007/3-540-39999-2_11openalex-snapshot
Processor Mechanisms for Software Shard Memory
inferred← citeshttps://doi.org/10.1007/3-540-44681-8_88openalex-snapshot
An Analytical Model of Deterministic Routing in the Presence of Hot-Spot Traffic
inferred← citeshttps://doi.org/10.1007/3-540-45307-5_17openalex-snapshot
Weld: A Multithreading Technique Towards Latency-tolerant VLIW Processors
inferred← citeshttps://doi.org/10.1007/978-1-4419-8987-1_16openalex-snapshot
Evaluating Novel Memory System Alternatives for Speculative Multithreaded Computer Systems
inferred← citeshttps://doi.org/10.1007/bfb0032689openalex-snapshot
Program optimization for concurrent multithreaded architectures
inferred← citeshttps://doi.org/10.1007/bfb0094912openalex-snapshot
Coping with very high latencies in petaflop computer systems
inferred← citeshttps://doi.org/10.1007/s10586-007-0021-zopenalex-snapshot
A queueing model for predicting message latency in uni-directional k-ary n-cubes with deterministic routing and non-uniform traffic
inferred← citeshttps://doi.org/10.1007/s10766-010-0162-1openalex-snapshot
An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs
inferred← citeshttps://doi.org/10.1016/j.sysarc.2003.09.008openalex-snapshot
On the performance of multicomputer interconnection networks
inferred← citeshttps://doi.org/10.1016/s0164-1212(03)00008-6openalex-snapshot
Analysis of true fully adaptive routing with software-based deadlock recovery
inferred← citeshttps://doi.org/10.1016/s0167-739x(02)00092-4openalex-snapshot
An analytical model of adaptive wormhole routing with time-out
inferred← citeshttps://doi.org/10.1023/b:supe.0000011387.24259.d1openalex-snapshot
Modeling Latency in Deterministic Wormhole-Routed Hypercubes under Hot-Spot Traffic
inferred← citeshttps://doi.org/10.1049/ip-cdt:20010251openalex-snapshot
Message latency in k-ary n-cubes with hop-based routing
inferred← citeshttps://doi.org/10.1109/12.795219openalex-snapshot
The superthreaded processor architecture
inferred← citeshttps://doi.org/10.1109/12.795220openalex-snapshot
Concurrent event handling through multithreading
inferred← citeshttps://doi.org/10.1109/71.914770openalex-snapshot
An analytical model of adaptive wormhole routing in hypercubes in the presence of hot spot traffic
inferred← citeshttps://doi.org/10.1109/arvlsi.1999.756051openalex-snapshot
VLSI architecture: past, present, and future
inferred← citeshttps://doi.org/10.1109/cahpc.2002.1180775openalex-snapshot
Exploiting loop-level parallelism with the Shift Architecture
inferred← citeshttps://doi.org/10.1109/csf51468.2021.00036openalex-snapshot
CapablePtrs: Securely Compiling Partial Programs Using the Pointers-as-Capabilities Principle
inferred← citeshttps://doi.org/10.1109/eeee.2009.64openalex-snapshot
Notice of Retraction: Student-Centric Evaluation Methodology for Teaching Effect of Teaching Methods in Computer Organization and Design Course
inferred← citeshttps://doi.org/10.1109/empdp.1999.746638openalex-snapshot
Matching architecture and software technology for HPC systems
inferred← citeshttps://doi.org/10.1109/fpga.2002.1106697openalex-snapshot
Mapping algorithms to the Amalgam programmable-reconfigurable processor
inferred← citeshttps://doi.org/10.1109/fpt.2002.1188674openalex-snapshot
Clustered programmable-reconfigurable processors
inferred← citeshttps://doi.org/10.1109/gpc.workshops.2008.25openalex-snapshot
Multicore Challenge in Pervasive Computing Education
inferred← citeshttps://doi.org/10.1109/hipc.1997.634466openalex-snapshot
Classification and performance evaluation of simultaneous multithreaded architectures
inferred← citeshttps://doi.org/10.1109/hpca.1998.650560openalex-snapshot
The impact of data transfer and buffering alternatives on network interface design
inferred← citeshttps://doi.org/10.1109/hpca.1998.650562openalex-snapshot
Exploiting two-case delivery for fast protected messaging
inferred← citeshttps://doi.org/10.1109/hpca.1999.744326openalex-snapshot
Supporting fine-grained synchronization on a simultaneous multithreading processor
inferred← citeshttps://doi.org/10.1109/hpca.2001.903262openalex-snapshot
Dynamic prediction of critical path instructions
inferred← citeshttps://doi.org/10.1109/hpca.2007.346182openalex-snapshot
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658652openalex-snapshot
An OS-based alternative to full hardware coherence on tiled CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2012.6168949openalex-snapshot
Design, integration and implementation of the DySER hardware accelerator into OpenSPARC
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522319openalex-snapshot
Runnemede: An architecture for Ubiquitous High-Performance Computing
inferred← citeshttps://doi.org/10.1109/iccd.1998.727091openalex-snapshot
The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline
inferred← citeshttps://doi.org/10.1109/iccd.2003.1240891openalex-snapshot
Routed inter-ALU networks for ILP scalability and performance
inferred← citeshttps://doi.org/10.1109/icpp.2001.952085openalex-snapshot
Performance modelling of a true fully adaptive routing algorithm
inferred← citeshttps://doi.org/10.1109/ict4m.2014.7090893openalex-snapshot
TOPAZ simulator on mesh and torus network
inferred← citeshttps://doi.org/10.1109/iitc.1999.787064openalex-snapshot
Interconnect-limited VLSI architecture
inferred← citeshttps://doi.org/10.1109/ipdps.2002.1016684openalex-snapshot
Comparative analysis of adaptive wormhole routing in Tori and hypercubes in the presence of hotspot traffic
inferred← citeshttps://doi.org/10.1109/ipdps.2005.108openalex-snapshot
Analytical Modelling of Hot-Spot Traffic in Deterministically-Routed K-Ary N-Cubes
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536357openalex-snapshot
Architecture optimizations for synchronization and communication on chip multiprocessors
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00068openalex-snapshot
CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities
inferred← citeshttps://doi.org/10.1109/ispa.2009.25openalex-snapshot
A Synchronization-Based Alternative to Directory Protocol
inferred← citeshttps://doi.org/10.1109/mascot.2001.948878openalex-snapshot
Analysis of timeout-based adaptive wormhole routing
inferred← citeshttps://doi.org/10.1109/pact.1996.552553openalex-snapshot
The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation
inferred← citeshttps://doi.org/10.1109/sc.2010.23openalex-snapshot
Exploiting 162-Nanosecond End-to-End Communication Latency on Anton
inferred← citeshttps://doi.org/10.1109/sec.2008.19openalex-snapshot
The Design of a Cycle Accurate Multi-core Architecture Performance Simulator
inferred← citeshttps://doi.org/10.1109/spdp.1996.570324openalex-snapshot
Comparison of two storage models in data-driven multithreaded architectures
inferred← citeshttps://doi.org/10.1109/tc.2009.96openalex-snapshot
CSMT: Simultaneous Multithreading for Clustered VLIW Processors
inferred← citeshttps://doi.org/10.1109/tpds.2005.150openalex-snapshot
High-performance and low-cost dual-thread VLIW processor using Weld architecture paradigm
inferred← citeshttps://doi.org/10.1109/tpds.2014.2307874openalex-snapshot
On-Chip Active Messages for Speed, Scalability, and Efficiency
inferred← citeshttps://doi.org/10.1145/1105734.1105742openalex-snapshot
Hardware-modulated parallelism in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1168857.1168897openalex-snapshot
Integrated network interfaces for high-bandwidth TCP/IP
inferred← citeshttps://doi.org/10.1145/1629395.1629403openalex-snapshot
Hybrid multithreading for VLIW processors
inferred← citeshttps://doi.org/10.1145/2145816.2145820openalex-snapshot
Efficient performance evaluation of memory hierarchy for highly multithreaded graphics processors
inferred← citeshttps://doi.org/10.1145/232973.232982openalex-snapshot
Evaluation of design alternatives for a multiprocessor microprocessor
inferred← citeshttps://doi.org/10.1145/263326.263382openalex-snapshot
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
inferred← citeshttps://doi.org/10.1145/279358.279399openalex-snapshot
Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor
inferred← citeshttps://doi.org/10.1145/3361682openalex-snapshot
Domain-specific hardware accelerators
inferred← citeshttps://doi.org/10.1145/511334.511343openalex-snapshot
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
inferred← citeshttps://doi.org/10.1145/564870.564912openalex-snapshot
A lightweight idempotent messaging protocol for faulty networks
inferred← citeshttps://doi.org/10.1145/641865.641867openalex-snapshot
A survey of processors with explicit multithreading
inferred← citeshttps://doi.org/10.1145/643114.643116openalex-snapshot
Parallel simulation of chip-multiprocessor architectures
inferred← citeshttps://doi.org/10.1504/ijhpcn.2005.007862openalex-snapshot
Trends toward on-chip networked microsystems
inferred← citeshttps://doi.org/10.2172/918315openalex-snapshot
A network architecture for Petaflops supercomputers.
inferred← citeshttps://doi.org/10.26634/jse.4.3.1112openalex-snapshot
Fault Tolerance and Reliability of Mesh Multi-computer Networks � A Review
inferred← citeshttps://doi.org/10.31274/rtd-180813-10743openalex-snapshot
Interprocessor communication in wormhole-switched multicomputers
inferred← citeshttps://doi.org/10.54097/ajst.v6i3.10512openalex-snapshot
Large-Scale Networked Visual Data: Current Research and Future Trends in Associative Inference and Semantic Comprehension
inferred← citeshttps://doi.org/10.5753/sbac-pad.2001.22197openalex-snapshot
A Technology-Scalable Multithreaded Architecture
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95098openalex-snapshot
Improving multithreading performance for clustered VLIW architectures.
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.