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The multiflow trace scheduling compiler
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4471-3501-2_9openalex-snapshot
Phase Ordering of Register Allocation and Instruction Scheduling
inferredcites →https://doi.org/10.1007/978-1-4613-1705-0openalex-snapshot
A Systolic Array Optimizing Compiler
inferredcites →https://doi.org/10.1016/0096-0551(81)90048-5openalex-snapshot
Register allocation via coloring
inferredcites →https://doi.org/10.1016/s0065-2458(08)60262-4openalex-snapshot
Supercomputer Performance: The Theory, Practice, and Results
inferredcites →https://doi.org/10.1109/12.2247openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/cmpcon.1991.128809openalex-snapshot
Architecture and compiler enhancements for PA-RISC workstations
inferredcites →https://doi.org/10.1109/superc.1988.44669openalex-snapshot
The Convex C240 architecture
inferredcites →https://doi.org/10.1109/superc.1990.130021openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.1109/superc.1990.130118openalex-snapshot
Architecture and implementation of a VLIW supercomputer
inferredcites →https://doi.org/10.1109/t-c.1970.222795openalex-snapshot
Detection and Parallel Execution of Independent Instructions
inferredcites →https://doi.org/10.1109/t-c.1972.223515openalex-snapshot
Percolation of Code to Enhance Parallel Dispatching and Execution
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1137/0211007openalex-snapshot
Symbolic Program Analysis in Almost-Linear Time
inferredcites →https://doi.org/10.1145/1014192.802448openalex-snapshot
Using an oracle to measure potential parallelism in single instruction stream programs
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/106972.106991openalex-snapshot
Limits of instruction-level parallelism
inferredcites →https://doi.org/10.1145/113445.113462openalex-snapshot
Register allocation via hierarchical graph coloring
inferredcites →https://doi.org/10.1145/12276.13312openalex-snapshot
Efficient instruction scheduling for a pipelined architecture
inferredcites →https://doi.org/10.1145/141868.141871openalex-snapshot
Performance of various computers using standard linear equations software
inferredcites →https://doi.org/10.1145/2166.357217openalex-snapshot
Postpass Code Optimization of Pipeline Constraints
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/29873.29875openalex-snapshot
Automatic translation of FORTRAN programs to vector form
inferredcites →https://doi.org/10.1145/3392717.3400034openalex-snapshot
Optimizing supercompilers for supercomputers
inferredcites →https://doi.org/10.1145/359060.359069openalex-snapshot
Global optimization by suppression of partial redundancies
inferredcites →https://doi.org/10.1145/36204.36193openalex-snapshot
How many addressing modes are enough?
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/502874.502896openalex-snapshot
Register allocation by priority-based coloring
inferredcites →https://doi.org/10.1145/567532.567555openalex-snapshot
Dependence graphs and compiler optimizations
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/68182.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/70082.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/7902.7904openalex-snapshot
Advanced compiler optimizations for supercomputers
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/88616.88621openalex-snapshot
The priority-based coloring approach to register allocation
inferredcites →https://doi.org/10.1145/93542.93553openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/960116.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/989393.989413openalex-snapshot
Efficient instruction scheduling for a pipelined architecture
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/989393.989433openalex-snapshot
Profile guided code positioning
inferredcites →https://doi.org/10.1147/rd.111.0025openalex-snapshot
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
inferredcites →https://doi.org/10.1147/rd.246.0695openalex-snapshot
The Experimental Compiling System
inferredcites →https://doi.org/10.1147/rd.341.0085openalex-snapshot
Instruction scheduling for the IBM RISC System/6000 processor
inferredcites →https://doi.org/10.1287/opre.9.3.383openalex-snapshot
A Proof for the Queuing Formula: L = λ W
inferredcites →https://doi.org/10.2172/5752434openalex-snapshot
Optimization of horizontal microcode within and beyond basic blocks: an application of processor scheduling with resources
inferredcites →https://doi.org/10.5555/110382.110438openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.5555/110382.110622openalex-snapshot
Architecture and implementation of a VLIW supercomputer
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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An Enhanced Trace Scheduler for SPARC Processors
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UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores
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Data dependence analysis of assembly code
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Predicated static single assignment
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Region formation analysis with demand-driven inlining for region-based optimization
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A unified compiler framework for control and data speculation
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Efficient backtracking instruction schedulers
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Efficient resource management during instruction scheduling for the EPIC architectures
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Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators
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Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach
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Architecture and technology tradeoffs in the design of next-generation multiprocessor servers
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CSMT: Simultaneous Multithreading for Clustered VLIW Processors
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Static Instruction Scheduling for High Performance on Limited Hardware
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Automatic Design Space Exploration of Register Bypasses in Embedded Processors
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RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions
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Retargetable pipeline hazard detection for partially bypassed processors
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Operation tables for scheduling in the presence of incomplete bypassing
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Design and evaluation of dynamic optimizations for a Java just-in-time compiler
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A region-based compilation technique for dynamic compilers
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Global instruction scheduling in dynamic compilation for embedded systems
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Instruction scheduling for a tiled dataflow architecture
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Instruction scheduling for a tiled dataflow architecture
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Instruction scheduling for a tiled dataflow architecture
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Instruction scheduling for a tiled dataflow architecture
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A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
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Dependence-based program analysis
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Lifetime-sensitive modulo scheduling
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Hybrid multithreading for VLIW processors
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Using a configurable processor generator for computer architecture prototyping
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Dependence-based program analysis
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Lifetime-sensitive modulo scheduling
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Avoidance and suppression of compensation code in a trace scheduling compiler
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Complexity/performance tradeoffs with non-blocking loads
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Complexity/performance tradeoffs with non-blocking loads
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Dynamic memory disambiguation for array references
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Improving the accuracy of static branch prediction using branch correlation
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Improving the accuracy of static branch prediction using branch correlation
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Mathematical foundation of trace scheduling
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Improving balanced scheduling with compiler optimizations that increase instruction-level parallelism
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Improving balanced scheduling with compiler optimizations that increase instruction-level parallelism
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A comparison of full and partial predicated execution support for ILP processors
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A comparison of full and partial predicated execution support for ILP processors
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A reduced multipipeline machine description that preserves scheduling constraints
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Fast, effective dynamic compilation
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Exploiting dual data-memory banks in digital signal processors
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Exploiting dual data-memory banks in digital signal processors
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Exploiting dual data-memory banks in digital signal processors
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A reduced multipipeline machine description that preserves scheduling constraints
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Fast, effective dynamic compilation
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