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CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-19426-6_10openalex-snapshot
A preliminary evaluation of a parallel inference machine for stream parallel languages
inferredcites →https://doi.org/10.1007/978-1-4471-3156-4_24openalex-snapshot
Overview of the Parallel Inference Machine Architecture (PIM)
inferredcites →https://doi.org/10.1007/978-1-4613-1619-0_3openalex-snapshot
Carmel-1: A VLSI Architecture for Flat Concurrent Prolog
inferredcites →https://doi.org/10.1109/40.16791openalex-snapshot
Implementation studies for a VLSI Prolog coprocessor
inferredcites →https://doi.org/10.1109/mc.1986.1663307openalex-snapshot
Concurrent Prolog: A Progress Report
inferredcites →https://doi.org/10.1109/mc.1987.1663695openalex-snapshot
A Survey of RISC Processors and Computers of the Mid-1980s
inferredcites →https://doi.org/10.1145/327070.327161openalex-snapshot
Performance studies of a Prolog machine architecture
inferredcites →https://doi.org/10.1145/327070.327163openalex-snapshot
Design of a high-speed Prolog machine (HPM)
inferredcites →https://doi.org/10.1145/5001.5390openalex-snapshot
PARLOG: parallel programming in logic
inferredcites →https://doi.org/10.1145/62959.62968openalex-snapshot
Garbarge collection for Prolog based on WAM
inferredcites →https://doi.org/10.5555/42040.42078openalex-snapshot
Architecture of high performance integrated Prolog processor IPP
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-56891-3_21openalex-snapshot
Monaco: A high-performance flat concurrent logic programming system
inferred← citeshttps://doi.org/10.1007/978-1-4471-3794-8_20openalex-snapshot
Sequentializing Parallel Programs
inferred← citeshttps://doi.org/10.1007/978-3-642-76799-9_10openalex-snapshot
The Family of Concurrent Logic Programming Languages
inferred← citeshttps://doi.org/10.1007/bf03037162openalex-snapshot
Sequential architecture models for Prolog: A performance comparison
inferred← citeshttps://doi.org/10.1007/bf03037178openalex-snapshot
UNIRED II: The high performance inference processor for the parallel inference machine PIE64
inferred← citeshttps://doi.org/10.1016/0743-1066(94)90031-0openalex-snapshot
1983–1993: The wonder years of sequential Prolog implementation
inferred← citeshttps://doi.org/10.1016/s0743-1066(96)00051-9openalex-snapshot
Experience with the Super Monaco optimizing compiler
inferred← citeshttps://doi.org/10.1016/s0743-1066(96)88981-3openalex-snapshot
Design and analysis of hardware for high-performance prolog
inferred← citeshttps://doi.org/10.1145/325096.325154openalex-snapshot
Fast Prolog with an extended general purpose architecture
inferred← citeshttps://doi.org/10.1145/72551.72555openalex-snapshot
The family of concurrent logic programming languages
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