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Sequential Prolog machine PEK

https://doi.org/10.1007/bf03037382
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf03037325openalex-snapshot
Towards a pipelined Prolog processor

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4613-1679-4_45openalex-snapshot
The Unification Processor by Pipeline Method
inferred← citeshttps://doi.org/10.1007/978-1-4613-1989-4_13openalex-snapshot
Overview of AI Application-Oriented Parallel Processing Research in Japan
inferred← citeshttps://doi.org/10.1007/978-3-7091-7533-0_32openalex-snapshot
Connectionist Unifying Prolog
inferred← citeshttps://doi.org/10.1007/978-94-009-5044-3_9openalex-snapshot
Hardware Architectures for Logic Programming
inferred← citeshttps://doi.org/10.1007/bf02943409openalex-snapshot
Improvements to the control techniques of sequential inference machines — From instructions to hardware organization
inferred← citeshttps://doi.org/10.1007/bf03037206openalex-snapshot
CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog
inferred← citeshttps://doi.org/10.1016/0165-6074(87)90049-4openalex-snapshot
Intermediate code for the sequential Prolog machine PEK
inferred← citeshttps://doi.org/10.1016/0165-6074(88)90133-0openalex-snapshot
A language coprocessor as a HLL directed architecture
inferred← citeshttps://doi.org/10.1016/0167-739x(87)90001-xopenalex-snapshot
POPE — a parallel-operating prolog engine
inferred← citeshttps://doi.org/10.1145/960114.29663openalex-snapshot
Implementation of a high-speed Prolog interpreter
inferred← citeshttps://doi.org/10.1145/98894.98940openalex-snapshot
Pipelined OR-parallelism architecture for parallel execution of Prolog
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